Zia Abbas

Impact of technology scaling on leakage power in nano-scale bulk CMOS digital standard cells

Leakage estimation is an important step in nano-scale technology digital design flows. While reliable data exist on leakage trends with bulk CMOS technology scaling in stand-alone devices and circuits, there is a lack of public domain results on the effect of scaling on leakage power consumption for a complete standard cell set. We present an analysis on a standard cell library applying a logic-level estimation model, supported by SPICE BSIM4 comparison. The logic-level model speedup over SPICE is >10^3 with average accuracy below 1% error. We therefore explore the effects of scaling on the whole standard cell set with respect to different leakage mechanisms (sub-threshold, body, gate) and to input pattern dependence. While body leakage appears to be dominant, sub-threshold leakage is expected to increase more than other components with scaling. Detailed data of the whole analysis are reported for use in further research on leakage aware digital design.

A Voltage-Based Leakage Current Calculation Scheme and its Application to Nanoscale MOSFET and FinFET Standard-Cell Designs

Logic-level estimators of leakage currents, in nanoscale standard-cell-based designs, are relevant for the dramatic speed advantage with respect to analog SPICE-level simulation. We propose a novel logic-level leakage estimation model based on the characterization of voltages at the internal nodes of digital cells, in conjunction with the characterization of leakage currents in a single field-effect transistor (FET) device and with the input-dependent Kirchhoff current law expression of the total current in the cell topology. The voltage-based nature of the approach simplifies the inclusion of supply voltage variation/scaling impact, as well as of output voltage drop (loading effect), on leakage currents. The method has been implemented in hardware description language models of a complete cell library. Exhaustive tests report average accuracy below 1% error in 22-nm CMOS and 20-nm FinFET technologies, when compared with SPICE BSIM simulation results.

Sizing and optimization of low power process variation aware standard cells

The yield of low voltage digital circuits based on standard cell design is found to be sensitive to local gate delay and power variations due to uncorrelated intra-die parameter fluctuations. Caused by random nature of doping positions they lead to more pronounced deviations for minimum transistor sizes. The basic idea of this work is to optimize the transistor level single standard cells by making the cells more resistant for process variations.

Design centering/yield optimization of power aware band pass filter based on CMOS current controlled current conveyor (CCCII+)

Process variability are getting worse with the scaled technologies especially below 90nm, therefore for the reliable fabrication outcome, the effect of both the local and global process variability should be taken into account. In this paper, verification, sizing and design centering/yield optimization for the robust second generation current controlled current conveyor (CCCII+) and CCCII+ based band pass filter for low power without degrading other performances values have been presented. Current conveyors (CC) based applications are getting significant attention in current analog ICs design due to their higher band-width, greater linearity, larger dynamic range, simpler circuitry, lower power consumption. Moreover CCCII has the advantage of electronic tunability at its intrinsic resistance terminal via a bias current. The net lists of CCCII+ and band pass filter circuits have been simulated in Eldo using the 65nm CMOS mixed signal low-K TSMC process development kit (PDK) with 1.2V, low-Vt devices with statistical models. All analysis, sizing and optimization have been performed using the WiCkeD^T^M tool at worst case operating conditions. Monte Carlo analysis has also been performed to verify the robustness of the circuit.

Optimal transistor sizing for maximum yield in variation-aware standard cell design

Summary Process variability, in addition to wide temperature and supply voltage variation ranges, severely degrades the fabrication outcome (yield) of digital cells as for the fulfillment of performance specification bounds. This paper presents the application of mathematical optimization to the design of standard cells that are robust to process variations even in worst-case operating conditions. The method attains the optimal sizing of individual transistors in the cell for maximizing the statistical yield referring to leakage power and propagation delay bounds, with local and global process variations specified by industrial process development kits (PDKs). The approach is demonstrated for a 40 nm low-power standard threshold voltage Complementary Metal Oxide Semiconductor (CMOS) technology, for an intended operating temperature range [−40 °C, 125 °C] and supply voltage range [0.95 V, 1.05 V]. The reported optimization results show a yield improvement from an initial 50% to 99.9%, and Simulation Program with Integrated Circuit Emphasis (SPICE)-level Monte Carlo analysis confirmed the estimated yield of the obtained circuits. Copyright

Yield optimization for low power current controlled current conveyor

Due to increasing CMOS process variability, optimization for yield has become one of the crucial tasks in Integrated Circuit (IC) design especially in analog IC design. This variability is getting worse with the continuous scaling of device dimensions and therefore degrades the IC fabrication outcome. This paper presents the yield optimization for low power second generation dual output current controlled current conveyor (DOCCCII). Current conveyors (CC) are getting significant attention in current analog ICs design due to their higher band-width, greater linearity, larger dynamic range, simpler circuitry, lower power consumption and less chip area. Moreover CCCII has the advantage of electronic tunability at its intrinsic resistance terminal via a bias current. The net list of given DOCCCII circuit has been simulated in Eldo using 65nm CMOS mixed signal Low-K IMD TSMC process development kit (PDK) with ±0.6V, low-Vt devices with statistical models. All verification, sizing and optimization analysis have been performed using the commercially available WiCkeD toolset from MunEDA at worst case operating conditions. Monte Carlo analysis has also been performed to verify the robustness of the circuit.

Optimal NBTI degradation and PVT variation resistant device sizing in a full adder cell

Aging phenomena, on top of process variations along with temperature and supply voltage variations, translate into complex degradation effects on the required performance and yield of nanoscale circuits. The proposed paper focuses on the development of mathematically optimal circuit sizing for yield maximization on the case study of a CMOS full adder circuit. The final cell design is robust against NBTI aging effects, impact of statistical (global and mismatch) and operating variation of temperature and supply voltage. Monte Carlo analysis has been carried out to verify the estimated yields. The demonstrated technique can be extended to a library of optimally designed digital cells.

Variability aware modeling of SEU induced failure probability of logic circuit paths in static conditions

Voltage noise can lead to various errors such as dynamic and permanent, which are directly associated to circuit-level reliability issues. Variability in process parameters directly affects the probability of failures associated to voltage noise. Yet, the evaluation of the probability of failures by SPICE level Monte Carlo simulation is prohibitively time-consuming. This work proposes a technique to characterize the input noise and process variations in order to estimate failure probability in a logic circuit path composed of combinational cells and registers. The method allows to correctly estimate the order of magnitude of the probability of failures and to evidence the influence of process variations, while reaching >104 speedup versus SPICE.