Andreas Wassatsch

DEPFET Active Pixel Detectors for a Future Linear

The DEPFET collaboration develops highly granular, ultra-transparent active pixel detectors for high-performance vertex reconstruction at future collider experiments. The characterization of detector prototypes has proven that the key principle, the integration of a first amplification stage in a detector-grade sensor material, can provide a comfortable signal to noise ratio of over 40 for a sensor thickness of 50-75 μm. ASICs have been designed and produced to operate a DEPFET pixel detector with the required read-out speed. A complete detector concept is being developed, including solutions for mechanical support, cooling, and services. In this paper, the status of the DEPFET R & D project is reviewed in the light of the requirements of the vertex detector at a future linear e+e- collider.

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ASTEROID is a new 64 channel ASIC developed to read out a DEPFET macropixel array. This sensor will be part of the MIXS instrument that will be used in the ESAs BepiColombo Mercury exploration mission. The detector will operate in an environment with high density of solar proton flux that will cause severe radiation damage and an increase of leakage current during mission lifetime. Given the relatively high value of the leakage current, a high speed readout and a proper cooling of the detector is needed in order to achieve the required energy resolution. The contribution of the readout electronics to the noise should be smaller than 10 electrons r.m.s. The foreseen pixel arrays are optimized for source follower readout. In this operating mode of the DEPFETs, the readout electronics is AC-coupled. This allows easy coping with non homogeneity of the pixel matrix and - most of all - an easy compensation of threshold voltage shifts of the DEPFET devices due to radiation damage. In order to achieve the low noise value required at short processing time, ASTEROID implements a trapezoidal weighting function, which represents the time-limited optimum filter for white series noise. This is the major electronics noise source at the foreseen readout speed. Measurements on a first prototype of the ASIC have shown the very satisfactory resolution of 147 eV on Mn-Kalphapeak of 55Fe with a readout time of approximately 1.2 mus, that would lead, considering the settling time of the DEPFET, to a total processing time of 4.2 mus. We present the experimental results of a first prototype that includes 4 analog channels and a new digital section for the generation of the timing signals of the circuit. This digital section is based on radiation- hardened dual-port memory cells and registers and has already been implemented to serve all the 64 channels foreseen for the final version of the ASIC.

Collider

We present the complete 64 channel version of the ASTEROID ASIC, developed to readout DEPFET Macro-Pixel Arrays operated in source follower mode. These sensors have been designed for the X-Ray Astronomy applications Simbol-X and BepiColombo. Both are satellite based missions that require a detector system with high speed readout, high energy resolution and radiation hardness properties. The foreseen baseline pixel arrays are optimized for source follower readout. In this operating mode of the DEPFETs, the readout electronics is AC-coupled. This allows easy coping with non homogeneity of the pixel matrix and an easy compensation of threshold voltage shifts of the DEPFET devices due to radiation damage. In order to achieve the low noise value required at short processing time, ASTEROID implements a trapezoidal weighting function. This filtering scheme substitutes the Multi-Correlated-Double-Sampling used so far by CAMEX ASICs and represents the time-limited optimum filter for white series noise, which is dominant at the foreseen readout speed. Measurements on single pixels had shown that an electronics noise as low as of about 8 electrons r.m.s. is achievable at room temperature with a total processing time of 4µs. In this work, preliminary measurements on the complete 64 channel readout ASIC coupled with a 64×64 DEPFET matrix have confirmed this noise performance. This result fits the requirements both of BepiColombo and Simbol-X. Also the other parameters of the ASIC have been tested on the 64 channel version. In order to fully operate the 64 channels in parallel, the ASIC contains a digital section that generates the timing signals for the analog circuits. This digital section is based on SEU-immune dual port memory cells. The outputs of the 64 analog channels are multiplexed to one serial output with a speed up to 20MHz. Thanks to the new multiplexer architecture adopted, ASTEROID will be the only ASIC that allows window-mode readout of the pixel matrices, i.e. that allows to address selectively arbitrary sub-areas of the pixel array or even to readout different sub-areas at different speeds.

ASTEROID: A new 64 channel ASIC for source follower based readout of the MIXS DEPFET arrays on BepiColombo

VERITAS (VErsatile Readout based on Integrated Trapezoidal Analog Shapers) is the first 128-channel ASIC developed to read out both the pnCCDs and the DEPFET arrays produced at the MPI-Halbleiterlabor in Munich. These detectors are used in a large variety of scientific applications, ranging from high-speed optical astronomy and X-ray astronomy to the new X-ray Free Electron Laser sources. The main concept of VERITAS is to provide a flexible readout chip able to cope not only with different kinds of detectors, but also with a large set of operating conditions that may require very different noise thresholds and input dynamic ranges. These can vary by more than two orders of magnitude. Every analog channel of VERITAS provides a trapezoidal weighting function. This filtering strategy had never been applied to the pnCCD before. The very first measurements obtained coupling VERITAS with a 128 × 256 pnCCD are shown. With a readout time of 4 μs/line a noise of 3.9 electrons has been measured in the highest gain mode. The resolution obtained on the Mn-Kα peak of a 55Fe source is 136 eV for single events. A noise of 30 electrons has been achieved in the lowest gain mode at a speed of 6.4 μs/line. In this low gain setting an input charge up to 2 5 × 105 electrons can be processed. These striking results fulfill the requirements of the main foreseen applications of large-size pnCCDs. In order to further improve the performance and the flexibility of the ASIC, a second version based on a fully differential architecture has been designed. The new topology allows one also to switch with the same ASIC between the source follower and drain current readout of the DEPFET sensors and to reach a processing time of about 2-3 μs/line with an electronics noise ≤10 el. For this reason the second version of VERITAS is very attractive for the proposed ESA X-ray astronomy mission ATHENA.

Performance of ASTEROID: A 64 channel ASIC for source follower readout of DEPFET matrices for X-ray astronomy

High-energy physics experiments require high-speed triggering systems capable of performing complex pattern recognition at rates of Megahertz to Gigahertz. Neural networks implemented in hardware have been the solution of choice for certain experiments. The neural triggering problem is presented here via a detailed look at the H1 level 2 trigger at the HERA accelerator, Hamburg, Germany, followed by a section on the importance of hardware preprocessing for such systems, and finally some new architectural ideas for using field programmable gate arrays in very high-speed neural-network triggers at upcoming experiments.

VERITAS: A 128-Channel ASIC for the Readout of pnCCDs and DEPFET Arrays for X-Ray Imaging, Spectroscopy and XFEL Applications

VERITAS 2.0 is a multi-channel readout ASIC for pnCCDs and DEPFET arrays. The main chip application is the readout of the DEPFET pixel arrays of the Wide Field Imager for the Athena mission. Every readout channel implements a trapezoidal weighting function and it is based on a fully differential architecture. VERITAS 2.0 is the first ASIC able to readout the DEPFETs both in source follower mode and in drain current mode. The drain readout should make it possible to achieve a processing time of about 2-3 μs/line with an electronics noise ≤ 5 electrons r.m.s.. The main concept and first measurements are presented.

Fast triggering in high-energy physics experiments using hardware neural networks

The new advancements in low-noise X-Ray detection pave the way to new space missions for deep space investigation like IXO. The concept of APS (Active Pixel Sensor) devices based on DEPFET (Depleted P-channel FET) structure has been developed to cope with the emerging requirements of low noise and high readout speed. Although the use of DEPFET makes achievable the required noise performance, it is necessary to develop a suitable front-end ASIC to fulfill the challenging speed requirements. We have developed VELA, a new fast multi-channel ASIC for the readout of a DEPFET matrix at high frame rate. The implemented circuit operates the DEPFET pixels in a drain current configuration to achieve a readout speed of 2 ¿s per line or even faster. The current version of VELA integrates 64 analog channels to readout a 64 × 64 DEPFET matrix up to 7800 frames per second. In the paper, the circuit and the working principle are presented; the VELA performance and the first measurement with a 64 × 64 DEPFET matrix are also reported.

VERITAS 2.0 a multi-channel readout ASIC suitable for the DEPFET arrays of the WFI for Athena

The DEPFET (DEPleted Field Effect Transistor) is an active pixel particle detector with a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) integrated in each pixel, providing first amplification stage of readout electronics. Excellent signal over noise performance is gained this way. The DEPFET sensor will be used as a vertex detector in the Belle II experiment at SuperKEKB, electron-positron collider in Japan. The vertex detector will be composed of two layers of pixel detectors (DEPFET) and four layers of strip detectors. The DEPFET sensor requires switching and current readout circuits for its operation. These circuits have been designed as ASICs (Application Specific Integrated Circuits) in several different versions, but they provide insufficient flexibility for precise detector testing. Therefore, a test system with a flexible control cycle range and minimal noise has been designed for testing and characterizing of small detector prototypes (Minimatrices). Sensors with different design layouts and thicknesses are produced in order to evaluate and select the one with the best performance for the Belle II application. Description of the test system as well as measurement results are presented.

First Readout of a 64

The new advancement in low-noise X-Ray detection paves the way to new space missions for deep space investigation, like SIMBOL-X. The concept of an APS (Active Pixel Sensor) based on DEPFET (Depleted P-channel FET) structure has been developed to cope with the emerging requirements. Although the use of DEPFET makes feasible to achieve the required noise performance, it is necessary to develop a suitable front-end ASIC to fulfill the challenging speed requirement.

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In this paper we describe an universal algorithm for data clustering on hardware level. By utilization of a software-inspired hardware architecture, the clustering task can be executed by a data clustering engine (DCE) in a pipelined data stream mode with a latency of only one frame. The scalable architecture of the clustering core allows a quick adaption of the engine to the specific needs of the target application. Furthermore, a prototype implementation in a TSMC 65nm low power CMOS process and an outlook on the final design for the Belle II experiment at KEK/Japan will be presented.