Giulio De Vita

Performance of ASTEROID: A 64 channel ASIC for source follower readout of DEPFET matrices for X-ray astronomy

We present the complete 64 channel version of the ASTEROID ASIC, developed to readout DEPFET Macro-Pixel Arrays operated in source follower mode. These sensors have been designed for the X-Ray Astronomy applications Simbol-X and BepiColombo. Both are satellite based missions that require a detector system with high speed readout, high energy resolution and radiation hardness properties. The foreseen baseline pixel arrays are optimized for source follower readout. In this operating mode of the DEPFETs, the readout electronics is AC-coupled. This allows easy coping with non homogeneity of the pixel matrix and an easy compensation of threshold voltage shifts of the DEPFET devices due to radiation damage. In order to achieve the low noise value required at short processing time, ASTEROID implements a trapezoidal weighting function. This filtering scheme substitutes the Multi-Correlated-Double-Sampling used so far by CAMEX ASICs and represents the time-limited optimum filter for white series noise, which is dominant at the foreseen readout speed. Measurements on single pixels had shown that an electronics noise as low as of about 8 electrons r.m.s. is achievable at room temperature with a total processing time of 4µs. In this work, preliminary measurements on the complete 64 channel readout ASIC coupled with a 64×64 DEPFET matrix have confirmed this noise performance. This result fits the requirements both of BepiColombo and Simbol-X. Also the other parameters of the ASIC have been tested on the 64 channel version. In order to fully operate the 64 channels in parallel, the ASIC contains a digital section that generates the timing signals for the analog circuits. This digital section is based on SEU-immune dual port memory cells. The outputs of the 64 analog channels are multiplexed to one serial output with a speed up to 20MHz. Thanks to the new multiplexer architecture adopted, ASTEROID will be the only ASIC that allows window-mode readout of the pixel matrices, i.e. that allows to address selectively arbitrary sub-areas of the pixel array or even to readout different sub-areas at different speeds.

Pixel readout ASIC with per pixel digitization and digital storage for the DSSC detector at XFEL

The DSSC collaboration is developing an instrument for the detection of synchrotron X-rays (E > 0.5 keV) at XFEL. The hexagonal pixels of a DEPFET based sensor with integrated signal compression will be read out by bump-bonded pixel readout ASICs. Each ASIC will have 64 × 64 pixel channels of 236 × 204 μm2 area, each one containing a low-noise (< 50 e−) amplification of the DEPFET signal, an 8 bit single-slope ADC and a digital memory, as well as other blocks for test injection, gain switching and trimming. Data is acquired during the XFEL burst at a rate of up to 4.5 MHz. The signal is first processed by a trapezoidal shaping filter, digitized immediately and then stored to the in-pixel memory of > 512 events capacity. The accumulated digital data is transferred off chip during the 100 ms long burst gaps on a single serial link while the analogue sections are shut down to bring the average power dissipation to < 100 mW per ASIC. The chip architecture is described and results obtained from first test chips are presented.

VERITAS 2.0 a multi-channel readout ASIC suitable for the DEPFET arrays of the WFI for Athena

VERITAS 2.0 is a multi-channel readout ASIC for pnCCDs and DEPFET arrays. The main chip application is the readout of the DEPFET pixel arrays of the Wide Field Imager for the Athena mission. Every readout channel implements a trapezoidal weighting function and it is based on a fully differential architecture. VERITAS 2.0 is the first ASIC able to readout the DEPFETs both in source follower mode and in drain current mode. The drain readout should make it possible to achieve a processing time of about 2-3 μs/line with an electronics noise ≤ 5 electrons r.m.s.. The main concept and first measurements are presented.

The wide-field imager for IXO: status and future activities

The Wide Field Imager (WFI) of the International X-ray Observatory (IXO) is an X-ray imaging spectrometer based on a large monolithic DePFET (Depleted P-channel Field Effect Transistor) Active Pixel Sensor. Filling an area of 10 x 10 cm2 with a format of 1024 x 1024 pixels it will cover a field of view of 18 arcmin. The pixel size of 100 x 100 μm2 corresponds to a fivefold oversampling of the telescopes expected 5 arcsec point spread function. The WFIs basic DePFET structure combines the functionalities of sensor and integrated amplifier with nearly Fano-limited energy resolution and high efficiency from 100 eV to 15 keV. The development of dedicated control and amplifier ASICs allows for high frame rates up to 1 kHz and flexible readout modes. Results obtained with representative prototypes with a format of 256 x 256 pixels are presented.

Fast, low-noise, low-power electronics for the analog readout of non-linear DEPFET pixels

A high speed focal plane system and a novel non linear DEPFET detector are under development to comply with the European X-ray Free Electron Laser (XFEL) requirements. The facility is under construction in the Hamburg area (Germany) and will be able to deliver ultra short, high intensity X-ray pulses 220ns apart and grouped in macro bunches with a repetition rate of 10Hz. DEPFETs have been chosen since they can provide excellent energy resolution and high speed readout. Full parallel readout is required, with every channel comprising analog filtering, data conversion and memory storage. Here we present results for the first prototype of the analog front end stage, that implements a current readout approach. The circuit is based on the Flip Capacitor Filter technique and was realized in 130nm 1.2V CMOS technology from IBM.

A 5MHz low-noise 130nm CMOS analog front-end electronics for the readout of non-linear DEPFET sensor with signal compression for the European XFEL

We present an integrated analog front-end for the readout of a non-linear DEPFET Sensor with Signal Compression (DSSC). The DSSC system, currently under development, is a 1-Mega pixel detector system for the European X-ray Free Electron Laser (XFEL) in Hamburg. It will record X-ray images with a maximum frame rate of 4.5MHz and will achieve at the same time a single photon resolution at 1keV and a high dynamic range. Two different readout strategies of the DEPFET pixel, Source Follower (SF) and Drain Readout (DR), have been fabricated in the 1.2V 0.13μm IBM CMOS technology. Both solutions share the same analog filter based on a new architecture that implements a trapezoidal shaping function employing only one operational amplifier. In this paper, the architecture of the analog front-end relative to both the readout strategies and of the new designed filter and the performance of the test chips are presented.

The IXO wide-field imager

The Wide Field Imager (WFI) of the International X-ray Observatory (IXO) is an X-ray imaging spectrometer based on a large monolithic DePFET (Depleted P-channel Field Effect Transistor) Active Pixel Sensor. Filling an area of 10 × 10 cm² with a format of 1024 × 1024 pixels it will cover a field of view of 18 arcmin. The pixel size of 100 × 100 μm² corresponds to a fivefold oversampling of the telescopes expected 5 arcsec point spread function. The WFIs basic DePFET structure combines the functionalities of sensor and integrated amplifier with nearly Fano-limited energy resolution and high efficiency from 100 eV to 15 keV. The development of dedicated control and amplifier ASICs allows for high frame rates up to 1 kHz and flexible readout modes. Results obtained with representative prototypes with a format of 256 × 256 pixels are presented.

64-channel ASTEROID ASIC: Experimental performance and measurements with Macro Pixel arrays for X-ray astronomy

The 64 channel ASTEROID ASIC has been designed to readout DEPFET pixel matrices for astronomy. In particular ASTEROID will be the readout ASIC of the DEPFET based Macro Pixel X-ray detector for the MIXS instrument on the European Mercury exploration mission BepiColombo. For this mission a detector system with high speed readout, high energy resolution and radiation hardness properties is required. Each of the 64 analog channels implements a trapezoidal weighting function. This is the optimum time limited filter for the white series noise, which is dominant at the foreseen readout speed. The ASIC is implemented in the 0.35 μm 3.3 V AMS CMOS technology. The spectroscopic performance of ASTEROID coupled with a 64×64 Macro Pixel array prototype with pixel area of 500×500 μm2 has been tested. An energy resolution of 128.5eV FWHM with the reconstruction of all split events has been measured on the Mn-ka of a 55Fe source operating ASTEROID with a total readout time of 4.8μs at -80ºC. Furthermore radiation hardness measurement on the digital section of the ASIC, both with a 10 MeV proton source and with a 5.5 MeV a particles source, proved the SEU immunity of the DICE based SRAM cells.

VERITAS: A 128-channel ASIC for the readout of pnCCDs and DEPFET arrays for X-ray imaging, spectroscopy and X-ray FEL applications. Experimental results and new designs

VERITAS is the first 128-channel ASIC developed to readout both the pnCCDs and the DEPFET arrays produced at the MPI-Halbleiterlabor in Munich. These detectors are used in a large variety of scientific applications, ranging from X-ray astronomy to the new X-ray Free Electron Laser sources. The main concept of VERITAS is to provide a flexible readout chip able to cope not only with different kinds of detectors, but also with a large set of operating conditions that may require very different noise thresholds and input dynamic ranges. These can vary by more than two orders of magnitude. Every analog channel of VERITAS provides trapezoidal weighting function. This filtering strategy had never been applied to the pnCCD before. The very first measurements obtained coupling VERITAS with a 128×256 pnCCD are shown. With these settings an input charge up to 2.5×105 electrons can be processed. With a readout time of 4 µs/line a noise of 3.9 electrons has been measured in the highest gain mode. The resolution obtained on the Mn-Kα peak of a 55Fe source is of 136 eV for single events. A noise of 30 electrons has been achieved in the lowest gain mode at a speed of 6.4 µs/line. In this low gain setting an input charge up to 2.5×105 electrons can be processed. These striking results fulfill the requirements of the main foreseen applications of large-size pnCCDs: experiments with Free Electron Lasers and high-speed optical astronomy. In order to further improve the performance and the flexibility of the ASIC, a second version based on a fully differential architecture has been designed. This topology allows a simpler filter implementation and it is less sensitive to cross-talk. In addition it offers the possibility to switch with the same ASIC between the source follower and drain current readout of the DEPFET sensors. The drain readout should make it possible to reach a processing time of about 2–3 µs/line with an electronics noise ≤10 el. This makes the second version of VERITAS very attractive for the proposed ESA X-ray astronomy mission ATHENA.

Integrated front-end readout electronics and analog filtering strategies for DEPFETs with special functionalities

DEPFET is a natural building block for pixel sensors as it comprises the properties of detector, amplifier and storage cell in a simple structure. DEPFET devices have been designed and fabricated with different topologies and their properties can be tailored according to the needs of different applications. In order to fully exploit the unique characteristics of the different DEPFETs, a suitable front-end integrated readout electronics and an ad-hoc filtering scheme must be adopted for every individual type of device and experiment. This work will focus on the front-end readout electronics for the Repetitive-Non-Destructive-Readout-DEPFET (RNDR-DEPFET) and for the Non-Linear DEPFET developed for XFEL in Hamburg. We present an optimized circuit and an optimized readout scheme that will allow reading out the two DEPFETS of the RNDR device simultaneously, reducing in this way the readout time of a factor 2. The proposed readout scheme constitutes the first step towards the development of a matrix of DEPFETs which can be operated in a complete parallel readout with a frame rate of some kHz. This readout speed, combined with the extremely low noise achieved, makes this system attractive for high-speed optical astronomy and adaptive optics. The DEPFET pixel array proposed for XFEL requires full parallel readout with a signal processing time not longer than 200ns, up to 10000 photons @1keV per-pixel and single photon resolution @1keV. Due to the very strict area constraints, a front-end readout electronics that provides amplification and Correlated Double Sampling in one single stage has been designed in a 130nm CMOS technology. The key properties of this circuit together with the expected noise performance will be discussed.