Andreia Cathelin

A 1 k-Pixel Video Camera for 0.7–1.1 Terahertz Imaging Applications in 65-nm CMOS

A 1 k-pixel camera chip for active terahertz video recording at room-temperature has been fully integrated in a 65-nm CMOS bulk process technology. The 32 × 32 pixel array consists of 1024 differential on-chip ring antennas coupled to NMOS direct detectors operated well-beyond their cutoff frequency based on the principle of distributed resistive self-mixing. It includes row and column select and integrate-and-dump circuitry capable of capturing terahertz videos up to 500 fps. The camera chip has been packaged together with a 41.7-dBi silicon lens (measured at 856 GHz) in a 5 × 5 × 3 cm3 camera module. It is designed for continuous-wave illumination (no lock-in technique required). In this video-mode the camera operates up to 500 fps. At 856 GHz it achieves a responsivity Rv of about 115 kV/W (incl. a 5-dB VGA gain) and a total noise equivalent power (NEPtotal) of about 12 nW integrated over its 500-kHz video bandwidth. At a 5-kHz chopping frequency (non-video mode) a single pixel can provide a maximum responsivity Rv of 140 kV/W (incl. a 5-dB VGA gain) and a minimum noise equivalent power ( NEP) of 100 pW/√Hz at 856 GHz. The wide-band antenna and pixel design achieves a 3-dB bandwidth of at least 790-960 GHz.

A 65-nm CMOS Fully Integrated Transceiver Module for 60-GHz Wireless HD Applications

This paper presents a fully integrated 60GHz transceiver module in a 65nm CMOS technology for wireless high-definition video streaming. The CMOS chip is compatible with the WirelessHD™ standard, covers the four channels and supports 16-QAM OFDM signals including the analog baseband. The ESD-protected die (9.3mm²) is flip-chipped atop a High Temperature Cofired Ceramic (HTCC) substrate, which receives also an external PA and the emission and reception glass-substrate antennas. The module occupies an area of only 13.5×8.5mm². It consumes 454mW in receiver mode and 1.357W in transmitter mode (357mW for the transmitter and 1W for the PA).

Nanoscale CMOS Transceiver Design in the 90–170-GHz Range

This paper reviews recent research conducted at the University of Toronto on the development of CMOS transceivers aimed at operation in the 90-170-GHz range. Unique nanoscale CMOS issues related to millimeter-wave circuit design in the 65-nm node and beyond are addressed with an emphasis on transistor and top-level layout issues, low-voltage circuit topologies, and design flow. A Doppler transceiver and two receivers fabricated in a 65-nm GPLP CMOS technology are described, along with a single pole, double throw antenna switch with better than 5-dB insertion loss and 25-dB isolation in the entire 110-170-GHz band. The first receiver has an IQ architecture with a fundamental frequency voltage-controlled oscillator, and is intended for wideband passive imaging applications at 100 GHz. The measured noise figure and downconversion gain are 7-8 and 10.5 dB, respectively, while the 3-dB bandwidth extends from 85 to 100 GHz. The second receiver has double-sideband architecture, operates in the 135-145-GHz range (the highest for CMOS receivers), and features an 8-dB gain LNA, a double-balanced Gilbert cell mixer, and a dipole antenna. The 90-94-GHz Doppler transceiver, the highest frequency reported to date in CMOS, is intended for the remote monitoring of respiratory functions. A Doppler shift of 30 Hz, produced by a slow-moving (4.8 cm/s) target located at a distance of 1 m, was measured with a transmitter output power of approximately + 2 dBm and a phase noise of -90 dBc/Hz at 1 MHz offset. The range correlation effect is demonstrated for the first time in CMOS by measuring the phase noise of the received baseband signal at 10-Hz offset, clearly indicating that 1/f noise has been canceled and it does not pose a problem in short-range applications, where neither a phase-locked loop nor a frequency divider are needed.

A G/sub m/-C low-pass filter for zero-IF mobile applications with a very wide tuning range

A third-order G/sub m/-C Butterworth low-pass filter implementing G/sub m/-tuning and G/sub m/-switching to maximize the tuning range is described. This filter is intended to be used as a channel-selection/anti-aliasing filter in the analog baseband part of a zero-IF radio receiver architecture for multimode mobile communications. Its G/sub m/-switching feature allows extending the tuning range and adapting the power consumption. The filters cutoff frequency ranges from 50 kHz to 2.2 MHz. An Input IP3 of up to +18 dBV/sub p/ is achieved, for a total worst-case power consumption of 7.3 mW for both I and Q paths, and an effective area of less than 0.5 mm/sup 2/ in a 0.25-/spl mu/m SiGe BiCMOS process. A new figure of merit is introduced for comparison of published low-pass tunable filters including noise, linearity, and tuning range.

A 3 GHz Dual Core Processor ARM Cortex TM -A9 in 28 nm UTBB FD-SOI CMOS With Ultra-Wide Voltage Range and Energy Efficiency Optimization

This paper presents the implementation details and silicon results of a 3 GHz dual-core ARM Cortex TM -A9 (A9) manufactured in the 28 nm planar Ultra-Thin Box and Body Fully-Depleted CMOS (UTBB FD-SOI) technology. The implementation is based on a fully synthesizable standard design flow. The design exploits the important flexibility provided by the FD-SOI technology, notably a wide Dynamic Voltage and Frequency Scaling (DVFS) range, from 0.52 V to 1.37 V, and Forward Body Bias (FBB) techniques up to 1.3 V. Detailed explanations of the body-biasing techniques specific to this technology are largely presented, in the context of a multi- VT co-integration, which enable this energy efficient silicon implementation. The system integrates all the advanced IPs for energy efficiency as well as the body bias generator and a fast (μs range) dynamic body bias management capability. The measured dual core CPU maximum operation frequency is 3 GHz (for 1.37 V) and it can be operated down to 300 MHz (for 0.52 V) in full continuous DVFS. The obtained relative performance, with respect to an equivalent planar 28 nm bulk CMOS chip, shows an improvement of +237% at 0.6 V, or +544% at 0.61 V with 1.3 V FBB.

An All-Digital RF Signal Generator Using High-Speed

An all-digital RF signal generator using DeltaSigma modulation and targeted at transmitters for mobile communication terminals has been implemented in 90 nm CMOS. Techniques such as redundant logic and non-exact quantization allow operation at up to 4 GHz sample rate, providing a 50 MHz bandwidth at a 1 GHz center frequency. The peak output power into a 100 Omega diff. load is 3.1 dBm with 53.6 dB SNDR. By adjusting the sample rate, carriers from 50 MHz to 1 GHz can be synthesized. RF signals up to 3 GHz can be synthesized when using the first image band. As an example, UMTS standard can be addressed by using a 2.6 GHz clock frequency. The measured ACPR is then 44 dB for a 5 MHz WCDMA channel at 1.95 GHz with output power of -16 dBm and 3.4% EVM. At 4 GHz clock frequency the total power consumption is 120 mW (49 mW for DeltaSigma modulator core) on a 1 V supply voltage, total die area is 3.2 mm2 (0.15 mm2 for the active area).

\Delta\Sigma

Future imaging applications in the submillimeter-Wave range (300GHz to 3THz) require RF systems that can achieve high sensitivity and portability at low power consumption levels. In particular, CMOS process technologies are attractive due to their low price tag for industrial, surveillance, scientific, and medical applications. Recently, CMOS-based detectors have shown good sensitivity up to 1THz with NEPs on the order of 66pW/√(Hz) at 1THz [1]. However, CMOS terahertz imagers developed thus far have only operated single detectors based on lock-in measurement techniques to acquire raster-scanned images with frame rates on the order of minutes [2]. To address these impediments, we present a low-power 1kpixel terahertz camera chip fully compliant with an industrial 65nm ft/fmax=160GHz/200GHz CMOS process technology. The active-pixel circuit topology is designed to accommodate the optics for wide bandwidth (0.6 to 1THz) in stand-off detection with a 40dBi Si-lens. It includes row/col select and integrate-and-dump circuitry capable of capturing terahertz images with video frame rates up to 25fps at a power consumption of 2.5μW/pixel.

Modulators

This paper presents a 1.2 V, 100 mW, 140 GHz receiver with on-die antenna in a 65 nm General Purpose (GP) CMOS process with digital back-end. The receiver has a conversion loss of 15-19 dB in the 100-140 GHz range with 102 GHz LO, and occupies a die area of only 580 mum times 700 mum including pads. The LNA achieves 8 dB gain at 140 GHz, 10 GHz bandwidth, at least -1.8 dBm of saturated output power, and maintains 3 dB gain at 125 degC. The on-chip antenna, which meets all density fill requirements of 65 nm CMOS, has -25 dB gain, and occupies 180 mum times 100 mum of die area. Additionally, design techniques which maximize the millimeter-wave performance of CMOS devices are discussed.

A 1kpixel CMOS camera chip for 25fps real-time terahertz imaging applications

With fast-growing demand for high-speed mobile communications and highly saturated spectral usage below 10GHz, mm-Wave frequency bands are emerging as the key playground for future high-data-rate wireless standards. Recent years have witnessed vast technology development on V-band (60GHz) Wireless Personal Area Networks (WPAN) and E-band (80GHz) point-to-point cellular backhauls. However, existing integrated CMOS mm-Wave solutions have relatively poor energy efficiency, especially for the transmitter (TX). This is mainly due to the use of traditional Class-A Power Amplifiers (PAs) that provide good linearity but suffer from low efficiency. In addition, the efficiency of Class-A PAs drop dramatically at power back-offs, making these transmitters even less efficient when conveying non-constant envelope signals. State-of-the-art mm-Wave Class-A PAs show less than 5% efficiency at 6dB back-off [1,2].

A 1.2V, 140GHz receiver with on-die antenna in 65nm CMOS

This paper presents a lens-integrated terahertz imaging detector implemented in a 65 nm bulk CMOS process technology. The back-side illumination through a silicon lens increases the imaging SNR by 7–15 dB. The broadband detector design has been verified from 0.6 to 1 THz. At 1 THz the circuit achieves a noise equivalent power (NEP) of 66 pW/√Hz and a responsivity (Rv) of 800 V/W for back-side illumination. The first 1 THz CMOS active imaging results with a lens are presented.