Andres Takach

An Introduction to High-Level Synthesis

The basic problem of high-level synthesis is the mapping of a behavioral description of a digital system into an RTL design consisting of a data path and a control unit. The authors introduce the FSMD model, which forms the basis for synthesis. They discuss the main considerations in a high-level synthesis environment: the input description language, the internal representation, and the main synthesis tasks-allocation, scheduling, and binding. They conclude with some problems that must be solved to make high-level synthesis a widely accepted methodology.<<ETX>>

C Based Hardware Design for Wireless Applications

The algorithms used in wireless applications are increasingly more sophisticated and consequently more challenging to implement in hardware. Traditional design flows require developing the micro architecture, coding the RTL, and verifying the generated RTL against the original functional C or MATLAB specification. This paper describes a C-based design flow that is well suited for the hardware implementation of DSP algorithms commonly found in wireless applications. The C design low relies on guided synthesis to generate the RTL directly from the untimed C algorithm. The specifics of the C-based design flow are described using a simple DSP filtering algorithm consisting of a forward adaptive equalizer, a 64-QAM slicer and an adaptive decision feedback equalizer. The example illustrates some of the capabilities and advantages offered by this flow.

Variation-aware resource sharing and binding in behavioral synthesis

As technology scales, the delay uncertainty caused by process variations has become increasingly pronounced in deep submicron designs. In the presence of process variations, worst-case timing analysis may lead to overly conservative synthesis, and may end up using excess resources to guarantee design constraints. In this paper, we propose an efficient variation-aware resource sharing and binding algorithm in behavioral synthesis, which takes into account the performance variations for functional units. The performance yield, which is defined as the probability that the synthesized hardware meets the target performance constraints, is used to evaluate the synthesis result. An efficient metric called statistical performance improvement, is used to guide resource sharing and binding. The proposed algorithm is evaluated within a commercial synthesis framework that generates optimized RTL netlists from behavioral specifications. The effectiveness of the proposed algorithm is demonstrated with a set of industrial benchmark designs, which consist of blocks that are commonly used in wireless and image processing applications. The experimental results show that our method achieves an average 33% area reduction over traditional methods, which are based on the worst-case delay analysis, with an average 10% run time overhead.

Guest Editors' Introduction: Raising the Abstraction Level of Hardware Design

Design complexity is continually rising with the higher levels of integration implied by Moores law. Functional complexity increases as more computation is added to SoCs and as more-complex applications are developed. Additional complexity is introduced by the need to control power consumption and to tackle challenges with respect to physical timing closure and process variations. To manage this complexity requires automation, letting designers focus on high-level design decisions that have the most effect in the implementations quality. A higher level of hardware design abstraction also enables an effective exploration of software and hardware architectures, making high-level synthesis a cornerstone of electronic system-level design. This special issue features nine articles that the authors believe will generate interest in the use of high-level synthesis and its further development.

Rapid industrial prototyping and SoC design of 3G/4G wireless systems using an HLS methodology

Many very-high-complexity signal processing algorithms are required in future wireless systems, giving tremendous challenges to real-time implementations. In this paper, we present our industrial rapid prototyping experiences on 3G/4G wireless systems using advanced signal processing algorithms in MIMO-CDMA and MIMO-OFDM systems. Core system design issues are studied and advanced receiver algorithms suitable for implementation are proposed for synchronization, MIMO equalization, and detection. We then present VLSI-oriented complexity reduction schemes and demonstrate how to interact these high-complexity algorithms with an HLS-based methodology for extensive design space exploration. This is achieved by abstracting the main effort from hardware iterations to the algorithmic C/C++ fixed-point design. We also analyze the advantages and limitations of the methodology. Our industrial design experience demonstrates that it is possible to enable an extensive architectural analysis in a short-time frame using HLS methodology, which significantly shortens the time to market for wireless systems.

Minimizing leakage power in aging-bounded high-level synthesis with design time multi- V th assignment

Aging effects (such as Negative Bias Temperature Instability (NBTI)) can cause the temporal degradation of threshold voltage of transistors, and have become major reliability concerns for deep-submicron (DSM) designs. Meanwhile, leakage power dissipation becomes dominant in total power as technology scales. While multi-threshold voltage assignment has been shown as an effective way to reduce leakage, the NBTI-degradation rates vary with different initial threshold voltage assignment, and therefore motivates the co-optimizations of leakage reduction and NBTI mitigation. This paper minimizes leakage power during high-level synthesis of circuits with bounded delay degradation (thus guaranteed lifetime), using multi-Vth resource libraries. We first propose a fast evaluation approach for NBTI-induced degradation of architectural function units, and multi-Vth resource libraries are built with degradation characterized for each function unit. We then propose an aging-bounded high-level synthesis framework, within which the degraded delays are used to guide the synthesis, and leakage power is optimized through the proposed aging-aware resource rebinding algorithm. Experimental results show that, the proposed techniques can effectively reduce the leakage power with an extra 26% leakage reduction, compared to traditional aging-unaware multi-Vth assignment approach.

High-Level Synthesis: Status, Trends, and Future Directions

The availability of increasing computational power in system-on-chips (SoCs) continues to drive the development of new and ever more complex applications. Hardware implementations of digital signal processing algorithms enable faster, lower power and less costly wireless, wired or optical fiber communication. It also enables the higher data compression, processing and analysis of image and video. The internet of things (IoT) is expected to further drive the development of sensors, data processing on those sensors, their interconnectivity within themselves and with data processing centers.

An introduction to the SystemC synthesis subset standard

High-level synthesis (HLS) offers the prospect of improving the productivity digital system design and the quality of the resulting implementations. Designing at higher levels of abstraction is a natural way for coping with system design complexity, for verifying earlier in the design process and for increasing design reuse. OSCIs synthesis working group (SWG) has led the effort of defining the synthesis subset for SystemC that is suitable for HLS. Draft version 1.3 of the document was released for public review in August 2009. While still in draft form, the released document provides guidance to both tool providers and users on the subset that is being proposed and the ability to provide feedback to the SWG on the draft. This tutorial will provide a brief introduction and three case studies on the use of HLS and the current SystemC synthesis subset draft for hardware design of digital systems.

Design and verification using high-level synthesis

The adoption of HLS has been driven by the need to tackle growing verification costs in traditional RTL design flows. This paper presents an overview of design, optimization and verification using HLS. It also outlines some of the requirements for HLS design to fit into existing design and verification flows and ways in which such flows might be adapted as HLS is more widely deployed.

Parametric yield-driven resource binding in high-level synthesis with multi- V th / V dd library and device sizing

The ever-increasing chip power dissipation in SoCs has imposed great challenges on todays circuit design. It has been shown that multiple threshold and supply voltages assignment (multi-Vth/Vdd) is an effective way to reduce power dissipation. However, most of the prior multi-Vth/Vdd optimizations are performed under deterministic conditions. With the increasing process variability that has significant impact on both the power dissipation and performance of circuit designs, it is necessary to employ statistical approaches in analysis and optimizations for low power. This paper studies the impact of process variations on the multi-Vth/Vdd technique at the behavioral synthesis level. A multi-Vth/Vdd resource library is characterized for delay and power variations at different voltage combinations. Meanwhile, device sizing is performed on the resources in the library to mitigate the impact of variation, and to enlarge the design space for better quality of the design choice. A parametric yield-driven resource binding algorithm is then proposed, which uses the characterized power and delay distributions and efficiently maximizes power yield under a timing yield constraint. During the resource binding process, voltage level converters are inserted between resources when required. Experimental results show that significant power reduction can be achieved with the proposed variation-aware framework, compared with traditional worstcase based deterministic approaches.