Adam P. Donlin

Evaluation of SystemC Modelling of Reconfigurable Embedded Systems

This paper evaluates the use of pin and cycle accurate SystemC models for embedded system design exploration and early software development. The target system is the MicroBlaze VanillaNet Platform running MicroBlaze uClinux operating system. The paper compares register transfer level (RTL) hardware description language (HDL) simulation speed to the simulation speed of several different SystemC models. It is shown that simulation speed of pin and cycle accurate models can go up to 150 kHz, compared to the 100 Hz range of HDL simulation. Furthermore, utilising techniques that temporarily compromise cycle accuracy, effective simulation speed of up to 500 kHz can be obtained.

FPGA Architecture Characterization for System Level Performance Analysis

We present a modular and scalable approach for automatically extracting actual performance information from a set of FPGA-based architecture topologies. This information is used dynamically during simulation to support performance analysis in a system level design environment. The topologies capture systems representing common designs using FPGA technologies of interest. Their characterization is done only once; the results are then used during simulation of actual systems being explored by the designer. Our approach allows a rich set of FPGA architectures to be explored accurately at various abstraction levels to seek optimized solutions with minimal effort by the designer. To offer an industrial example of our results, we describe the characterization process for Xilinx Core Connect-based platforms and the integration of this data into the METROPOLIS modeling environment

A Virtual File System for Dynamically Reconfigurable FPGAs

Platform FPGAs have dramatically changed the role of FPGAs in embedded systems. With increased density and immersed complex IPs, FPGAs no longer simply play ‘a role’ in embedded systems – FPGAs are embedded systems. To accommodate the increased system capability of Platform FPGAs, they also host a rich embedded software environment. Embedded Linux has emerged as a common software infrastructure for embedded systems in general and is also being employed in FPGA-based embedded systems.

SystemC for the Design and Modeling of Programmable Systems

The Field Programmable Logic (FPL) community is set to assume an important role within the electronic system level (ESL) community. Programmable technologies are proving to be the correct implementation substrate for the growing majority of system architects who can no longer afford the cost or shoulder the risks associated with sub-micron ASIC design. In this tutorial we present an overview of SystemC, the dominant and open environment for ESL design and modeling. We focus on presenting the fundamentals of the language and describing an important extension to the language that enables rapid modeling of systems at the transaction level.

You can catch more bugs with transaction level honey

In this special session we explore holistic approaches to hardware/software debug that use or integrate transaction level models (TLMs). We present several TLM-based approaches to system-level diagnostics, ranging from use of most popular transaction level modeling languages through to hybrid technologies that combine TLMs with other well known diagnostic tools like in-silicon trace logic.

New tool support and architectures in adaptive reconfigurable computing

Novel methods and reconfigurable architectures provide an increased design space by exploiting the dynamic and partial reconfiguration of hardware. The multi-adaptivity of this heterogeneous reconfigurable architectures reaches from adaptation to performance requirements over adaptation to power consumption in relation to an available amount of energy to adaptation to not predictable requirements from the user. Especially the unpredictable demands and requirements to a computing architecture require a high and filigree adaptivity in order to find an optimized point of operation while run- time. Additional to this issue the increased availability of electronic systems comes by introduction of novel methods for failure redundancy which can be seen as an application of this multi-adaptive system. In this contribution the ideas for a novel system approach will be presented in three parts. First the hardware and methods providing the multi-adaptivity will be presented. This is the basis for higher level design tools and opens a variety of parameters for adaptivity. The mechanisms of reconfigurability will be introduced in detail from basic knowledge to advanced mechanisms and methods. In addition the abstraction levels for manipulation the reconfigurable architecture and points to the tool support for novel reconfigurable FPGA architectures from Xilinx are sketched.

From ESL 2010 to ESL 2015

In 2010, a wave of consolidation swept over the Electronic System Level (ESL) design industry. It brought ESL providers together with mainstream EDA houses and created opportunities for new ESL ventures. This paper contains short summaries of presentations in a special session focusing on the future of ESL. The session has two goals: the first is to present the state of the art in ESL tools and practice and, second, share a vision of the technical challenges that the next generation of ESL companies should address. The session includes a mix of perspectives from both ESL solution vendors and end-users and touches all all four ESL use cases: software virtual platforms, performance analysis, high level synthesis and verification.

PROGRAMMABLE PLATFORM CHARACTERIZATION FOR SYSTEM LEVEL PERFORMANCE ANALYSIS

It is customary to begin a discussion of Electronic System Level (ESL) design by stating at least one of the following observations [7]: • Time-to-market is a major influence on the design of most electronic systems; • Design complexity has outpaced designer productivity; • Verification effort now dominates design effort; • Custom design costs too much to be practical for most designs; • Register Transfer Level (RTL) design methods will not scale to address the design complexity; • Designers must work at higher levels of design abstraction to overcome design complexity; • Design re-use will be necessary to overcome design complexity. Figure 1 presents a graph relating design complexity to designer productivity with both RTL and ESL design methods. Today, most designers work with RTL design tools and languages. They find themselves in the ‘design gap’ where the system they are trying to create exceeds the capabilities of their design environment. This is not to say that the design gap cannot be crossed. On the contrary, the gap can be overcome with existing design methods but only at a significantly increased cost (both financially [5], [6] and in designer effort). Existing RTL design methods will continue to be employed until the additional cost of design overwhelms the