Andrew C. Rudack

TSOM Method for Semiconductor Metrology

Through-focus scanning optical microscopy (TSOM) is a new metrology method that achieves 3D nanoscale measurement sensitivity using conventional optical microscopes; measurement sensitivities are comparable to what is typical when using scatterometry, scanning electron microscopy (SEM), and atomic force microscopy (AFM). TSOM can be used in both reflection and transmission modes and is applicable to a variety of target materials and shapes. Nanometrology applications that have been demonstrated by experiments or simulations include defect analysis, inspection and process control; critical dimension, photomask, overlay, nanoparticle, thin film, and 3D interconnect metrologies; line-edge roughness measurements; and nanoscale movements of parts in MEMS/NEMS. Industries that could benefit include semiconductor, data storage, photonics, biotechnology, and nanomanufacturing. TSOM is relatively simple and inexpensive, has a high throughput, and provides nanoscale sensitivity for 3D measurements with potentially significant savings and yield improvements in manufacturing.

Film quantum yields of EUV& ultra-high PAG photoresists

Base titration methods are used to determine C-parameters for three industrial EUV photoresist platforms (EUV- 2D, MET-2D, XP5496) and twenty academic EUV photoresist platforms. X-ray reflectometry is used to measure the density of these resists, and leads to the determination of absorbance and film quantum yields (FQY). Ultrahigh levels of PAG show divergent mechanisms for production of photoacids beyond PAG concentrations of 0.35 moles/liter. The FQY of sulfonium PAGs level off, whereas resists prepared with iodonium PAG show FQYs that increase beyond PAG concentrations of 0.35 moles/liter, reaching record highs of 8-13 acids generated/EUV photons absorbed.

Photons, electrons, and acid yields in EUV photoresists: a progress report

This paper describes our initial investigation into building a greater understanding of the complex mechanism occurring during extreme ultraviolet (EUV) exposure of resist materials. In particular, we are focusing on the number and energy of photoelectrons generated and available for reaction with photoacid generators (PAGs). We propose that this approach will best enable the industry to develop resists capable of meeting resolution, line width roughness (LWR), and sensitivity requirements.

Sub‐imaging Techniques For 3D‐Interconnects On Bonded Wafer Pairs

The semiconductor industrys ability to follow Moores law to continue to increase the number of components on integrated circuits is increasingly difficult. One way to improve the product performance even at decreased footprint is the use of 3D interconnects which stacks multiple chips in a single package. This new technology for connecting chips overcomes some of the limitations of 2D interconnects. For example, 3D interconnects significantly reduce interconnect delay and improve clock distribution. At the same time that research into 3D technology such as Through Silicon Vias (TSVs) is advancing quickly, the microscopy techniques used in the evaluation of TSV must also advance in capability. Void inspection after copper plating, defect detection and overlay measurements after wafer bonding are challenging. Microscopy techniques for which silicon is opaque such as scanning acoustic microscope (SAM) and confocal infrared microscope (IR) are capable of inspecting the interface between bonded wafer pairs, ...

Infrared microscopy for overlay and defect metrology on 3D-interconnect bonded wafers

Microscopy of 3D interconnect structures is challenged by the opaque nature of silicon. Infrared (IR) microscopy provides a way of “seeing” through the silicon where microscopes based on visible wavelengths fail. IR microscopy is used in 3D manufacturing to image sub-surface features (alignment fiducials, defects, and voids) at the interface of bonded wafers. This practical solution enables a variety of through-silicon metrology, including overlay alignment, (e.g., metal 2 to via), review of pre-existing defects from each wafer at the bond interface, and detection of new defects created during the bonding process. IR microscopy is a non-destructive technique and, as such, is an ideal candidate for the in-line metrology required to inspect and monitor the 3D through-silicon via (TSV) interconnect process. This paper reviews the overlay and defect metrology capabilities of IR microscopy. The ability to measure the overlay alignment of bonded wafers according to the 2009 International Technology Roadmap for Semiconductors (ITRS) [1] is demonstrated. Overlay tolerances for a variety of copper interconnect test structures are predicted based on electrical designs, and overlay results are compared to electrical test results. Defect review of bonded wafers is accomplished by “flipping” the defect coordinate system for inverted wafers. The ramifications of adding new defect data to bonded wafer defect files are discussed. The use of IR microscopy to measure wafer pair overlay and to study the interface defectivity of bonded wafer pairs is clearly demonstrated.

Inspection and metrology for through-silicon vias and 3D integration

3D IC integration employs advanced interconnect technologies including through-silicon vias (TSVs), bonding, wafer thinning, backside processing and fine pitch multi-chip stacking. In 2013, Mobile Wide I/O DRAM is expected to be one of the first high volume 3D IC applications. Many of the manufacturing steps in TSV processing and 3D integration can complicate inspection and metrology. This paper reviews a typical via-mid flow emphasizing the inspection and metrology challenges inherent in 3D integration. A preliminary look at the 2011 ITRS roadmap for 3D interconnect metrology is presented, including the gaps in currently available inspection and metrology tools.

Induced ESD damage on photomasks: a reticle evaluation

An Electric-field (E-field) exposure tool for Photomasks was designed, assembled, then utilized to subject 250 nanometer technology node reticles to variable electric fields. A similar study had been demonstrated using the Canary Reticle. The goal was to induce an Electrostatic Discharge (ESD), and attempt to damage the reticles chrome structures via the Field Induced Damage Model. Electrostatic Discharge emits a radio wave in the 100 MHz to 2.0 GHz frequency range, which can be detected using a Digital Sampling Oscilloscope and antenna. Once detected via radio wave sampling techniques, the Field Induced Damage is evaluated on a KLA STARlight inspection tool, and a damage map provided. A Digital Instruments Atomic Force Microscope utilizes the damage map to locate defects for further evaluation.

Thermally induced void growth in through-silicon vias

Abstract. Thermally induced void growth in Cu filled through-silicon vias (TSV) has been studied for reliability purposes with x-ray microscopy and finite element model (FEM). A laboratory-based x-ray microscopy combined with computational tomography imaging is demonstrated to have advantages over other methods of inspecting TSVs. We show that the 8-keV x-rays used by Nano X-ray Computed Tomography (NanoXCT™) are capable of imaging voids inside filled vias before and after annealing without cross-sectioning the TSV. A series of TSV arrays filled conformally and from the bottom up were inspected by the x-ray microscope before and after annealing. Pre-existing voids in the seamline were observed in conformally filled TSVs before annealing, while bottom up-filled TSVs do not have a seamline or voids. The same TSV samples were repeatedly annealed at 200, 225, 250 and 300°C. X-ray micrographs after annealing reveal TSVs with pre-existing voids are prone to void growth. In addition, x-ray measurements show the total volume of void growth increased with annealing temperature. A steady-state FEM was developed to understand the void growth phenomenon. FEM suggests high concentrations of vacancies occurring at the pre-existing void area cause void growth.

Wafer placement repeatibility and robot speed improvements for bonded wafer stacks used in 3D integration

Robotic wafer handling of bonded wafer stacks (BWS) brings new challenges in placement repeatability and robot speed. Current standard SEMI M1.15 [1] does not contemplate wafer stacks >775 microns thick. Varying BWS thickness of 800-microns (top wafer thinned to 25-microns bonded to a 775 micron carrier wafer) to 1550 microns thick (two full thickness 775 micron wafers bonded together) creates additional mass and thus additional momentum during wafer movement. Without a corresponding increase in holding force, wafer sliding on the end effector is likely. One solution is to reduce robot velocity and acceleration, but this can lead to tool throughput reductions. In this paper we explore wafer handling issues for BWS and the application of a new end effector technology, called Gravity Edge Hold (GEH). Wafer sliding issues will be described in terms of wafer and BWS momentum, lateral holding force, and robot acceleration. It will further describe the wafer placement repeatability issues encountered and the corresponding decrease in robot speeds implemented to counteract this problem. Laboratory experiments were conducted to compare the performance of traditional end effectors used in current 300mm tools to that of the GEH end effector. An evaluation based on lateral holding force is included.

Mask damage by electrostatic discharge: a reticle printability evaluation

An evaluation of a Photolithography Mask damaged by Electrostatic Discharge (ESD) is presented, using pictures and data from the toolset at International SEMATECHs Advanced Technology Development Facility. The Photomask used in the printability evaluation is the Canary (DuPont TM) Reticle, demonstrating various degrees of ESD-induced damage to a repeating structure contained in the chrome-on-quartz pattern. Levels of damage to the chrome structures vary from non-existent, to barely detectable, to moderate, to catastrophic. The ESD-induced damage is then measured and compared through an assortment of Mask Metrology tools.