Andrew Cofler

A reprogrammable EDGE baseband and multimedia handset SoC with 6-mbit embedded DRAM

A CMOS EDGE baseband and multimedia handset SoC features a dual core (microcontroller and DSP) architecture together with all the necessary interface logic and hardware accelerators interconnected by a multi-layer bus. The DSP memory hierarchy features an instruction cache coupled to a 6-Mbit embedded DRAM instruction memory allowing in the field software flexibility (for example dynamic upgrade of DSP software), while minimizing power and area (closely matching a ROM based solution). The chip is implemented in a 130-nm 6-metal layer CMOS process and is packaged in a 12 /spl times/ 12 ball-grid array. Full chip standby mode current is 690 /spl mu/A (with data retention), resulting in a 500 hour complete GSM/EDGE terminal autonomy.A 0.13 /spl mu/m 6M CMOS EDGE baseband and multimedia handset SoC features a 6 Mb embedded-DRAM DSP instruction memory to allow dynamic upgrade of DSP software, such as applications downloaded from the network. Full-chip standby current is 690 /spl mu/A which gives 500 h complete GSM/EDGE terminal autonomy when using an 800 mAh battery.