Francois Druilhe

A reprogrammable EDGE baseband and multimedia handset SoC with 6-mbit embedded DRAM

A CMOS EDGE baseband and multimedia handset SoC features a dual core (microcontroller and DSP) architecture together with all the necessary interface logic and hardware accelerators interconnected by a multi-layer bus. The DSP memory hierarchy features an instruction cache coupled to a 6-Mbit embedded DRAM instruction memory allowing in the field software flexibility (for example dynamic upgrade of DSP software), while minimizing power and area (closely matching a ROM based solution). The chip is implemented in a 130-nm 6-metal layer CMOS process and is packaged in a 12 /spl times/ 12 ball-grid array. Full chip standby mode current is 690 /spl mu/A (with data retention), resulting in a 500 hour complete GSM/EDGE terminal autonomy.A 0.13 /spl mu/m 6M CMOS EDGE baseband and multimedia handset SoC features a 6 Mb embedded-DRAM DSP instruction memory to allow dynamic upgrade of DSP software, such as applications downloaded from the network. Full-chip standby current is 690 /spl mu/A which gives 500 h complete GSM/EDGE terminal autonomy when using an 800 mAh battery.

A second-generation modem analog front-end

The echo-cancelling voice-grade modems used on PSTN are projected to increase in bit rate from the present 14.4 kb/s (V.32bis) to 19.2 kb/s and even 24 kb/s in the near future. This will be facilitated by increasing the symbol rate from 2400 baud to maximum of 3200 baud, but will cost a 3-dB increase in dynamic range for every 2.4 kb/s increment. Improvement of 12 to 18 dB in dynamic range and linearity is required for the modem analog front-end (MAFE) described. The modem block diagram presented gives the worst-case magnitudes of the signals in the duplexer performing two-wire/four-wire conversion. The demodulator receives a signal between -3 dBm and -43/-48 dBm corrupted by a -9 dBm local echo. After echo removal, the signal-to-noise ratio must reach 25 dB to 35 dB for good performance at 19.2 kb/s, 30 dB to 40 dB at 24 kb/s, depending on the line quality. It is demonstrated that the second-order sigma-delta analog-to-digital converter used in the MAFE is consistent with this goal, taking into account the 12-dB peak factor of the quadrature amplitude modulation used in high-speed single-carrier modems.<<ETX>>