Andrew Geissler

Energyscale for IBM POWER6 microprocessor-based systems

With increasing processor speed and density, denser system packaging, and other technology advances, system power and heat have become important design considerations. The introduction of new technology including denser circuits, improved lithography, and higher clock speeds means that power consumption and heat generation, which are already significant problems with older systems, are significantly greater with IBM POWER6™ processor-based designs, including both standalone servers and those implemented as blades for the IBM BladeCenter® product line. In response, IBM has developed the EnergyScale™ architecture, a system-level power management implementation for POWER6 processor-based machines. The EnergyScale architecture uses the basic power control facilities of the POWER6 chip, together with additional board-level hardware, firmware, and systems software, to provide a complete power and thermal management solution. The EnergyScale architecture is performance aware, taking into account the characteristics of the executing workload to ensure that it meets the goals specified by the user while reducing power consumption. This paper introduces the EnergyScale architecture and describes its implementation in two representative platform designs: an eight-way, rack-mounted machine and a server blade. The primary focus of this paper is on the algorithms and the firmware structure used in the EnergyScale architecture, although it also provides the system design considerations needed to support performance-aware power management. In addition, it describes the extensions and modifications to power management that are necessary to span the range of POWER6 processor-based system designs.

Power-performance management on an IBM POWER7 server

The processor and cooling subsystems of high-performance servers consume a significant portion of total system power. In this paper, we use the server energy-efficiency benchmark SPECpower ssj2008 to assess dynamic power management strategies for these sub-systems on an IBM POWER 750 platform. First, we evaluate the impact of feedback-driven fan control to reduce power while continuously maintaining a suitable thermal environment. Next, we demonstrate the importance of refining traditional utilization-based DVFS algorithms when managing systems with large core and thread counts. We present a new approach and demonstrate its effectiveness with real-world scenarios for dynamic power management. With reliable runtime power management, we can safely boost (turbo) core frequencies beyond their nominal values to achieve higher throughput. The combined effect of dynamic fan and enhanced processor DVFS control yields an overall improvement of 43% for the energy-efficiency score of the SPECpower ssj2008 benchmark on our test system.