Malcolm S. Allen-Ware

Active management of timing guardband to save energy in POWER7

Microprocessor voltage levels include substantial margin to deal with process variation, system power supply variation, workload induced thermal and voltage variation, aging, random uncertainty, and test inaccuracy. This margin allows the microprocessor to operate correctly during worst-case conditions, but during typical conditions it is larger than necessary and wastes energy. We present a mechanism that reduces excess voltage margin by (1) introducing a critical path monitor (CPM) circuit that measures available timing margin in real-time, (2) coupling the CPM output to the clock generation circuit to adjust clock frequency within cycles in response to excess or inadequate timing margin, and (3) adjusting the processor voltage level periodically in firmware to achieve a specified average clock frequency target. We implemented this mechanism in a prototype IBM POWER7 server. During better-than-worst case conditions our guardband management mechanism reduces the average voltage setting 137–152 mV below nominal, resulting in average processor power reduction of 24% with no performance loss while running industry-standard benchmarks.

Introducing the Adaptive Energy Management Features of the Power7 Chip

Power7 implements several new adaptive power management techniques which, in concert with the EnergyScale firmware, let it proactively exploit variations in workload, environmental conditions, and overall system use to meet customer-directed power and performance goals. These innovative features include per-core frequency scaling with available autonomic frequency control, per-chip automated voltage slewing, power consumption estimation, and hardware instrumentation assist.

TAPO: Thermal-aware power optimization techniques for servers and data centers

A large portion of the power consumption of data centers can be attributed to cooling. In dynamic thermal management mechanisms for data centers and servers, thermal setpoints are typically chosen statically and conservatively, which leaves significant room for improvement in the form of improved energy efficiency. In this paper, we propose two hierarchical thermal-aware power optimization techniques that are complementary to each other and achieve (i) lower overall system power with no performance penalty or (ii) higher performance within the same power budget.

Active Guardband Management in Power7+ to Save Energy and Maintain Reliability

Microprocessor voltage levels traditionally include substantial margin to ensure reliable operation despite variations in manufacturing, workload, and environmental parameters. This margin allows the microprocessor to function correctly during worst-case conditions, but during typical operation it is larger than necessary and wastes energy. The authors present a mechanism that reduces excess voltage margin by introducing a critical-path monitor (CPM) circuit that measures available timing margin in real time; coupling the CPM output to the clock generation circuit to rapidly adjust clock frequency in response to excess or inadequate timing margin; and adjusting the processor voltage level periodically in firmware to achieve a specified average clock frequency target. They first demonstrated this mechanism in an IBM Power7 server and proved its effectiveness in the Power7+ product. Power consumption on the VDD rail was reduced by 11 percent for SPEC CPU2006 workloads with negligible performance loss yet increased protection against noise events.

Accurate Fine-Grained Processor Power Proxies

There are not yet practical and accurate ways to directly measure core power in a microprocessor. This limits the granularity of measurement and control for computer power management. We overcome this limitation by presenting an accurate runtime per-core power proxy which closely estimates true core power. This enables new fine-grained microprocessor power management techniques at the core level. For example, cloud environments could manage and bill virtual machines for energy consumption associated with the core. The power model underlying our power proxy also enables energy-efficiency controllers to perform what-if analysis, instead of merely reacting to current conditions. We develop and validate a methodology for accurate power proxy training at both chip and core levels. Our implementation of power proxies uses on-chip logic in a high-performance multi-core processor and associated platform firmware. The power proxies account for full voltage and frequency ranges, as well as chip-to-chip process variations. For fixed clock frequency operation, a mean unsigned error of 1.8% for fine-grained 32ms samples across all workloads was achieved. For an interval of an entire workload, we achieve an average error of-0.2%. Similar results were achieved for voltage-scaling scenarios, too. We also present two sample applications of the power proxy: (1) per-core power billing for cloud computing services, and (2) simultaneous runtime energy saving comparisons among different power management policies without running each policy separately.

Temperature-Aware Architecture: Lessons and Opportunities

Managing temperature has become an important concern in modern processor and other microelectronic chips. The problem has become especially severe as the ability to reduce supply voltage has slowed. As a result, the number of devices per unit area is sca ing up faster than the power density is scaling down. This requires more expensive cooling solutions to keep the chip and its local hotspots cool, and these challenges will be exacerbated by 3D integration, which seems imminent. Furthermore, high temperature slows integrated circuits because of degraded carrier mobility and interconnect resistivity. It also accelerates multiple chip-failure mechanisms such as electromigration and negative bias temperature instability (NBTI), because the wearout rate has an exponential temperature dependency. Static leakage power is primarily an exponential function of temperature. Theres also the possibility of thermally induced security vulnerabilities, such as denial of service. Unfortunately, air coolings ability to address temperature concerns is limited by system-level power constraints, acoustic challenges, and sometimes form factors, while alternative cooling solutions are still too expensive for commodity use. Temperature-aware design can reduce these problems.

Robust power management in the IBM z13

The power management strategy adopted for the IBM z13™ processor chip (referred to as the CP or Central Processor chip) is guided by three basic principles: (a) controlling the peak power consumption by setting a realistic limit on the so-called thermal design power or thermal design point (TDP) driven by customer workloads and maximum-power stress microbenchmarks; (b) reduction of the voltage margin by using a novel dynamic guard-banding technique; and (c) the creation of a rich new set of fine-grained, time-synchronized sensors that track performance, power, temperature, and power management behavior for a running machine. A prime requirement of the power management architecture is that the efficient control mechanisms be designed in such a manner that the high standards of IBM z Systems™ application performance and reliability be maintained without any compromise. In this paper, we describe the key features constituting the z13 CP robust power management architecture and design that meet the stipulated objectives.

BCID: An effective data center power mapping technology

The mapping of the power delivery network to the equipment in a data center is an essential step towards having intelligent and efficient control over data center power distribution. Visual identification of the power connectivity is error-prone and expensive while other methods require high-power signal injection and significant human labor or interruption in the power delivery, making them impractical. The use of power modulation in a server has been proposed but requires large power variations in order to do the mapping. In this paper we propose a new technique that reduces by over an order of magnitude the amount of signaling power necessary to less than 2.5W. Using this technique we show that a simple, USB device is able to generate that signal, allowing a non-intrusive method to identify the power connectivity for a system. The speed of detecting the connectivity reliably makes this a feasible solution for mapping entire data centers.