Andrew K. Bolstad

Smart pixel imaging with computational-imaging arrays

Smart pixel imaging with computational-imaging arrays (SPICA) transfers image plane coding typically realized in the optical architecture to the digital domain of the focal plane array, thereby minimizing signal-to-noise losses associated with static filters or apertures and inherent diffraction concerns. MIT Lincoln Laboratory has been developing digitalpixel focal plane array (DFPA) devices for many years. In this work, we leverage legacy designs modified with new features to realize a computational imaging array (CIA) with advanced pixel-processing capabilities. We briefly review the use of DFPAs for on-chip background removal and image plane filtering. We focus on two digital readout integrated circuits (DROICS) as CIAs for two-dimensional (2D) transient target tracking and three-dimensional (3D) transient target estimation using per-pixel coded-apertures or flutter shutters. This paper describes two DROICs – a SWIR pixelprocessing imager (SWIR-PPI) and a Visible CIA (VISCIA). SWIR-PPI is a DROIC with a 1 kHz global frame rate with a maximum per-pixel shuttering rate of 100 MHz, such that each pixel can be modulated by a time-varying, pseudorandom, and duo-binary signal (+1,-1,0). Combining per-pixel time-domain coding and processing enables 3D (x,y,t) target estimation with limited loss of spatial resolution. We evaluate structured and pseudo-random encoding strategies and employ linear inversion and non-linear inversion using total-variation minimization to estimate a 3D data cube from a single 2D temporally-encoded measurement. The VISCIA DROIC, while low-resolution, has a 6 kHz global frame rate and simultaneously encodes eight periodic or aperiodic transient target signatures at a maximum rate of 50 MHz using eight 8-bit counters. By transferring pixel-based image plane coding to the DROIC and utilizing sophisticated processing, our CIAs enable on-chip temporal super-resolution.

Identification and compensation of Wiener-Hammerstein systems with feedback

Efficient operation of RF power amplifiers requires compensation strategies to mitigate nonlinear behavior. As bandwidth increases, memory effects become more pronounced, and Volterra series based compensation becomes onerous due to the exponential growth in the number of necessary coefficients. Behavioral models such as Wiener-Hammerstein systems with a parallel feedforward or feedback filter are more tractable but more difficult to identify. In this paper, we extend a Wiener-Hammerstein identification method to such systems showing that identification is possible (up to inherent model ambiguities) from single- and two-tone measurements. We also calculate the Cramér-Rao bound for the system parameters and compare to our identification method in simulation. Finally, we demonstrate equalization performance using measured data from a wideband GaN power amplifier.

An active filter achieving 43.6dBm OIP 3

An active filter with a 50 Ω buffer suitable as an anti-alias filter to drive a highly linear ADC is implemented in 0.13 µm SiGe BiCMOS. This 6^th-order Chebyshev filter has a 3 dB cutoff frequency of 28.3 MHz and achieves 36.5 dBm OIP<inf>3</inf>. Nonlinear digital equalization further improves OIP<inf>3</inf> to 43.6 dBm. Measurements show 92 dB of rejection at the stopband and a gain of 49 dB. The measured in-band OIP<inf>3</inf> of 43.6 dBm is 19 dB higher than previously published designs.

Low Power Sparse Polynomial Equalizer (SPEQ) for Nonlinear Digital Compensation of an Active Anti-Alias Filter

We present an efficient architecture to perform on-chip non-linear equalization of an anti-alias RF filter. The sparse polynomial equalizer (SPEq) achieves substantial power savings through co-design of the equalizer and the filter, which allows including the right number of processing elements, filter taps, and bits to maximize performance and minimize power consumption. The architecture was implemented in VHDL and fabricated in CMOS 65 nm technology. Testing results show that undesired spurs are suppressed to near the noise floor, improving the systems spur-free dynamic range by 25 dB in the median case, and consuming less than 12 mW of core power when operating at 200 MHz.

Sparse volterra systems: Theory and practice

Nonlinear effects limit analog circuit performance, causing both in-band and out-of-band distortion. The classical Volterra series provides an accurate model of many nonlinear systems, but the number of parameters grows extremely quickly as the memory depth and polynomial order are increased. Recently, concepts from compressed sensing have been applied to nonlinear system modeling in order to address this issue. This work investigates the theory and practice of applying compressed sensing techniques to nonlinear system identification under the constraints of typical radio frequency (RF) laboratories. The main theoretical result shows that these techniques are capable of identifying sparse Memory Polynomials using only single-tone training signals rather than pseudorandom noise. Empirical results using laboratory measurements of an RF receiver show that sparse Generalized Memory Polynomials can also be recovered from two-tone signals.

Physical layer considerations for wideband cognitive radio

Next generation cognitive radios will benefit from the capability of transmitting and receiving communications waveforms across many disjoint frequency channels spanning hundreds of megahertz of bandwidth. The information theoretic advantages of multi-channel operation for cognitive radio (CR), however, come at the expense of stringent linearity requirements on the analog transmit and receive hardware. This paper presents the quantitative advantages of multi-channel operation for next generation CR, and the advanced digital compensation algorithms to mitigate transmit and receive nonlinearities that enable broadband multi-channel operation. Laboratory measurements of the improvement in the performance of a multi-channel CR communications system operating below 2 GHz in over 500 MHz of instantaneous bandwidth are presented.

Practical sub-Nyquist sampling via array-based compressed sensing receiver architecture

This paper introduces the Array-based Compressed sensing Receiver Architecture (ACRA). ACRA allows digital receiver arrays to operate at dramatically larger instantaneous bandwidths by sampling the signals from different array elements at different sub-Nyquist sampling rates. Signal processing inspired by the sparse fast Fourier transform allows for signal detection, estimation, and angle-of-arrival determination. Simulation results and measurements from an 18-45 GHz testbed are presented.

An array-based compressed sensing receiver architecture

This paper describes an Array-based Compressed sensing Receiver Architecutre (ACRA) which allows a digital receiver array to drastically increase its instantaneous bandwidth to detect, estimate, and determine angle of arrival of signals which are sparse in frequency or angle-frequency space. ACRA intentionally aliases the wideband signal at each element of the array, but uses different sampling rates at different antennas. The unique aliasing patterns produced at each channel can be used to determine the true frequencies of received signals using the sparse fast Fourier transform or similar algorithms. The concept is demonstrated using an 8-channel testbed targeting the 18–50 GHz band. The analog to digital converters in the testbed have a maximum sampling rate of 2 GSPS; thus the testbed demonstrates the potential for a sixteen fold increase in bandwidth when in-phase and quadrature sampling is used.

Biquad implementation of an IIR filter for IQ mismatch correction in an SoC RF receiver

This paper presents an IQ mismatch correction design and implementation that is part of a system-on-chip (SoC) that also includes a homodyne RF receiver and a sparse nonlinear equalizer. It uses IIR filters to help the RF receiver achieve greater than an 80 dB image rejection ratio. The IIR filters are implemented using biquad structures to minimize power consumption by limiting the number of bits used per tap. The design was implemented in 65 nm CMOS technology and it is estimated to have a power performance of 150 GOPS per watt.

Sparse polynomial equalization of an RF receiver via algorithm, analog, and digital codesign

Nonlinear circuit behavior degrades system performance of RF receivers operating near the compression point, causing both in-band and out-of-band distortions. Linearity can be improved through analog design changes at the cost of greater power consumption. Alternatively, digital compensation algorithms can alleviate nonlinear distortions, but standard combinatorial models of nonlinear system behavior can require high-power digital circuits. We present preliminary results of a co-optimized receiver and digital equalizer achieving 80 dB spurious free dynamic range over 49 MHz while dissipating 132 mW. We describe the codesign process used to optimize power consumption across analog and digital circuits while meeting high linearity requirements.