Karen Gettings

Test Circuit for Study of CMOS Process Variation by Measurement of Analog Characteristics

We propose and demonstrate a test chip for extraction of spatial and layout dependent variations in both transistor and interconnect structures. A scan chain approach is combined with low-leakage and low-variation switches, providing access to detailed analog device characteristics in large arrays of test devices. Compared to digital test structures such as ring oscillators, the test circuit enables flexible extraction and analysis of variation in any device model parameters based on current-voltage measurements.

Study of CMOS Process Variation by Multiplexing Analog Characteristics

Aggressive technology scaling raises the need for efficient methods to characterize and model circuit variation at both the front and back end of line, where critical parameters such as threshold voltage and parasitic capacitance must be carefully modeled for accurate circuit performance. In this paper we address this need by contributing a test circuit methodology for the extraction of spatial, layout and size dependent variations at both device and interconnect levels. The test chip uses a scan chain approach combined with low-leakage and low-variation switches, and Kelvin sensing connections, providing access to detailed analog device characteristics in large arrays of test devices. Variation measurement using the designed test chip has proven successful for both device and interconnect test structures. The parameter extraction and variation analyses made possible by the variation test chip enable the identification of likely variation sources, quantification of circuit impact and sensitivity, and specification of layout practices for variation minimization.

Low Power Sparse Polynomial Equalizer (SPEQ) for Nonlinear Digital Compensation of an Active Anti-Alias Filter

We present an efficient architecture to perform on-chip non-linear equalization of an anti-alias RF filter. The sparse polynomial equalizer (SPEq) achieves substantial power savings through co-design of the equalizer and the filter, which allows including the right number of processing elements, filter taps, and bits to maximize performance and minimize power consumption. The architecture was implemented in VHDL and fabricated in CMOS 65 nm technology. Testing results show that undesired spurs are suppressed to near the noise floor, improving the systems spur-free dynamic range by 25 dB in the median case, and consuming less than 12 mW of core power when operating at 200 MHz.

Optical physical unclonable function

Many military and commercial systems require a unique digital identification for authentication, key derivation, and other purposes. Our approach uses an optical physical unclonable function (PUF) that can be implemented on printed circuit boards (PCB). Various environmental factors, such as physical stress, temperature, heat dissipation, and aging, affect the effectiveness of such a PUF. This paper will discuss our recent research in addressing these and other concerns by advancing in the areas of waveguide construction, system longevity, and PCB cooling. We will also discuss the enhanced capability of differentiating between intact and disturbed systems.

Fabrication security and trust of domain-specific ASIC processors

Application specific integrated circuits (ASICs) are commonly used to implement high-performance signal-processing systems for high-volume applications, but their high development costs and inflexible nature make ASICs inappropriate for algorithm development and low-volume DoD applications. In addition, the intellectual property (IP) embedded in the ASIC is at risk when fabricated in an untrusted foundry. Lincoln Laboratory has developed a flexible signal-processing architecture to implement a wide range of algorithms within one application domain, for example radar signal processing. In this design methodology, common signal processing kernels such as digital filters, fast Fourier transforms (FFTs), and matrix transformations are implemented as optimized modules, which are interconnected by a programmable wiring fabric that is similar to the interconnect in a field programmable gate array (FPGA). One or more programmable microcontrollers are also embedded in the fabric to sequence the operations. This design methodology, which has been termed a coarse-grained FPGA, has been shown to achieve a near ASIC level of performance. In addition, since the signal processing algorithms are expressed in firmware that is loaded at runtime, the important application details are protected from an unscrupulous foundry.

SHAMROCK: A Synthesizable High Assurance Cryptography and Key management coprocessor

For performance, maintainability and usability, military communications systems must properly integrate and coordinate cryptographic primitives and use adequate key management schemes. In this paper, we present a SHAMROCK (Synthesizable High Assurance Management/Reservation/Operation of Cryptography and Keys) coprocessor. Being self-contained and synthesizable, SHAMROCK empowers designers to readily and correctly incorporate cryptography and key management into embedded systems. SHAMROCK has been incorporated in multiple mission critical systems to enable secure computing and communications.

Coarse-grain reconfigurable ASIC through multiplexer based switches

We present an ASIC architecture with coarse-grain reconfigurability that uses accelerators to improve performance over fine-grain reconfigurable architectures. A reconfigurable FFT ASIC was built as a proof of concept, and it successfully demonstrated valid switch operation for reconfiguration.

Biquad implementation of an IIR filter for IQ mismatch correction in an SoC RF receiver

This paper presents an IQ mismatch correction design and implementation that is part of a system-on-chip (SoC) that also includes a homodyne RF receiver and a sparse nonlinear equalizer. It uses IIR filters to help the RF receiver achieve greater than an 80 dB image rejection ratio. The IIR filters are implemented using biquad structures to minimize power consumption by limiting the number of bits used per tap. The design was implemented in 65 nm CMOS technology and it is estimated to have a power performance of 150 GOPS per watt.

Sparse polynomial equalization of an RF receiver via algorithm, analog, and digital codesign

Nonlinear circuit behavior degrades system performance of RF receivers operating near the compression point, causing both in-band and out-of-band distortions. Linearity can be improved through analog design changes at the cost of greater power consumption. Alternatively, digital compensation algorithms can alleviate nonlinear distortions, but standard combinatorial models of nonlinear system behavior can require high-power digital circuits. We present preliminary results of a co-optimized receiver and digital equalizer achieving 80 dB spurious free dynamic range over 49 MHz while dissipating 132 mW. We describe the codesign process used to optimize power consumption across analog and digital circuits while meeting high linearity requirements.