Andrew T. Yang

Stable and efficient reduction of substrate model networks using congruence transforms

Parasitic analog-digital noise coupling has been identified as a key issue facing designers of mixed-signal integrated circuits. In particular signal cross talk through the common chip substrate has become increasingly problematic. The paper demonstrates a new methodology for developing simulation, synthesis, and verification models to analyze the global electrical behavior of the non-ideal semiconductor substrate. RC substrate network models, which are generated via a triangular discretization method, are accurately approximated for subsequent analysis by an efficient reduction algorithm. This algorithm utilizes the well-conditioned Lanczos process to formulate Pade approximations of the network port admittance. Congruence transformations are employed to ensure stability, and to create reduced networks which are easily realizable with SPICE-compatible RC elements. For validation, the strategy has been successfully applied to several mixed-signal circuit examples.

Integrated circuit substrate coupling models based on Voronoi tessellation

We present a modeling technique for assessing the impact of substrate-coupled switching noise in CMOS mixed-signal circuits. Since the magnitude of the noise problem is a function of the relative proximity of noisy and sensitive devices, design aids are required which can incorporate the switching noise effects at the post-layout phase of design verification. In our approach, SPICE-compatible lumped element RC substrate macromodels are efficiently generated from the circuit layout using a geometric construct called the Voronoi tessellation. The new models retain the accuracy of previously reported models, but contain orders of magnitude fewer circuit nodes, and are suitable for analyzing larger circuits. The node count reduction is realized by deriving a model topology which automatically adapts itself to the local densities of substrate features associated with the noise coupling. Our strategy has been verified using detailed 2-D device simulation, and successfully applied to some mixed-A/D circuit examples.

iSMILE: A Novel Circuit Simulation Program with emphasis on New Device Model Development

The laborious task of implementing a new device model in a circuit simulator has long been recognized as a painful bottleneck to device modeling. In contrast to the conventional circuit simulators which employ a built-in model library approach, iSMILE generates and links all the necessary codes automatically from a minimal set of model descriptions contained in a users model input file. Users are completely shielded from the internal complexity of the program when implementing new models. This flexibility of extraction and by comparing circuit simulation results in terms of performance and accuracy. iSMILE has been used successfully as a CAD tool for the development of new models for high-speed optoelectronic integrated circuits.

Interconnect characterization using time-domain reflectometry

An approach is presented for modeling board-level, package-level, and multichip module substrate-level interconnect circuitry based on measured time-domain reflectrometry data. The scattering poles and residues of a multiport system are extracted and used as a model that can be evaluated in linear time by recursive convolution in a SPICE-based simulator. This allows any linear or nonlinear circuits to be connected to the model ports, and the entire circuit may be simulated in in a SPICE-based simulator. Two-port and four-port example microstrip circuits are characterized, and the simulation results are compared with measured data. Delay, reflection, transmission, and crosstalk are shown to be accurately modeled in each case. >

Stable and efficient reduction of large, multiport RC networks by pole analysis via congruence transformations

A novel technique is presented which employs Pole Analysis via Congruence Transformations (PACT) to reduce RC networks in a well-conditioned manner. Pole analysis is shown to be more efficient than Pade approximations when the number of network ports is large, and congruence transformations preserve the passivity (and thus absolute stability) of the networks. Networks are represented by admittance matrices throughout the analysis, and this representation simplifies interfacing the reduced networks with circuit simulators as well as facilitates realization of the reduced networks using RC elements, A prototype SPICE-in, SPICE-out, network reduction CAD tool called RCFIT is detailed, and examples are presented which demonstrate the accuracy and efficiency of the PACT algorithm.

Mixed-Signal Switching Noise Analysis Using Voronoi-Tessellated Substrate Macromodels

We present a new modeling technique for analyzing the impact of substrate-coupled switching noise in CMOS mixed-signal circuits. Lumped element RC substrate macromodels are efficiently generated from layout using Voronoi tessellation. The models retain the accuracy of previously proposed models, but contain orders of magnitude fewer circuit nodes, and are suitable for analyzing large-scale circuits. The modeling strategy has been verified using detailed device simulation, and applied to some mixed-A/D circuit examples.

An efficient nonquasi-static diode model for circuit simulation

Based on the partitioned-charge-based modeling approach, a general nonquasi-static dynamic charge element is derived to simulate both transient behavior and high-frequency characteristics of a semiconductor diode. A new model parameter /spl tau/ is introduced to describe the dynamic charge redistribution time for a diode. By partitioning the total base charge into quasi-static (QS) and nonquasi-static (NQS) terms, a single-/spl tau/ (level 2) diode model is first derived. By further dividing the NQS charge, a double-/spl tau/ (level 3) diode model is proposed to describe different reverse recovery processes. In addition, a voltage-dependent equation is incorporated to the double-/spl tau/ model into account for the dynamic charge partitioning. We show that the SPICE diode (level 1) model is included by setting /spl tau/ to zero as a special case of the proposed models. The new diode model has been implemented in MISIM, a model independent SPICE-like simulation framework. Significant improvement in accuracy over the traditional SPICE diode model in both time and frequency domain has been demonstrated, while achieving the same or even better simulation speed and reliability. >

Simulation of high-frequency integrated circuits incorporating full-wave analysis of microstrip discontinuities

Incorporates full-wave simulation of microstrip interconnects into circuit analysis and shows how predicted responses diverge from those based on models from a modern microwave-circuit CAD package. A method is presented for characterizing microstrip interconnects and discontinuities through the method of moments applied to a mixed-potential integral equation. The speed is greatly improved through the use of a recently published techniques for rapid evaluation of microstrip spatial Greens functions. A microstrip circuit element is analyzed separately with this procedure, and scattering parameters are extracted from the computed current density. These parameters are passed to a circuit simulator, where small- and large-signal analyses reveal how differences in interconnect modeling affect predicted responses. >

Modeling and simulation of higb-frequency integrated circuits based on scattering parameters

We ~esent an approach for accurate modeling and simulation of high-frequency circuits. This capability results from 1) efficient determina tion of scattering matrices of microstrip interconnects using Prony’s method and nonlinear optimization for the evaluation of Som,erfeld integrals, 2) extraction of a generalized charge-based FET model from scattering parameter data and 3) an improved harmonic ba@we technique based on the Newton Projection method. These novel techniques have been integrated into MISIM, a flexible CAD system for design verification and rapid teclmology characterization.

Delay modeling and timing of bipolar digital circuits

An approach for timing simulation of bipolar ECL (emitter-coupled-logic) digital circuits is described. The approach is based on the development of a switch-level model of the transistor and on the representation of the circuit by a switch graph. The circuit is partitioned into subcircuits, and symbolic logic expressions are generated which represent the logic states of the nodes in terms of subcircuit inputs and initial conditions. Timing information is computed using an analytical delay model which relates outputs of a subcircuit to its input waveforms. The model includes the effects of the transistor SPICE parameter model as well as the circuit parameters. The combination of the switch-level graph model and the delay model provides fast and accurate timing simulation of ECL circuits. In addition, the switch-graph model provides a unified way for simulating BIMOS circuits.<<ETX>>