Daniel G. Saab

Structural and behavioral synthesis for testability techniques

In this paper, a behavioral synthesis for testability system is presented. In this system, a testability modifier is connected to an existing behavioral level synthesis program, which accepts a circuits behavioral description in C or VHDL as input. The outline of the system is as follows: (1) a testability analyzer is first applied to identify the hard-to-test areas in the circuit from the behavioral description; (2) a selection process is then applied to select test points or partial scan flip-flops. Selection is based on behavioral information rather than low-level structural description. This allows test point insertion or partial scan usage on circuits described as an interconnection of high level modules; (3) test statement insertion (TSI), an alternative to test point insertion and partial scan, is used to modify the circuit based on the selected test points. The major advantage of using TSI is a low pin count and test application time as compared to test point insertion and partial scan. In addition, TSI can be applied at the early design phase. This approach was implemented in a computer program, and applied to several sample circuits generated by a synthesis tool. The results are also presented. >

Satisfiability on reconfigurable hardware

In this paper we present a new approach to implement satisfiability (SAT) on reconfigurable hardware. Given a combinational circuit C, we automatically design a SAT circuit whose architecture implements a branch-and-bound SAT algorithm specialized for C. A major novel feature is that both the next variable to assign and its value are dynamically determined by a backward model traversal done in hardware. Our approach relies on fine-grain massive parallelism.

Application of simple genetic algorithms to sequential circuit test generation

In this work we investigate the effectiveness of genetic algorithms (GAs) in the test generation process. We use simple GAs to generate populations of candidate test vectors and to select the best vector to apply in each time frame. A sequential circuit fault simulator is used to evaluate the fitness of each candidate vector, allowing the test generator to be used for both combinational and sequential circuits. We experimented with various GA parameters, namely population size, number of generations, mutation rate, and selection and crossover schemes. For the ISCAS85 combinational benchmark circuits, 100% of testable faults were detected in six of the ten circuits used, and very compact test sets were generated. Good results were obtained for many of the ISCAS89 sequential benchmark circuits, and execution times were significantly lower than in a deterministic test generator in most cases.<<ETX>>

VLSI logic and fault simulation on general-purpose parallel computers

The authors define a general framework for the parallel simulation of digital systems and develop and evaluate tools for logic and fault simulation that have a good cost-performance ratio. They first review previous work and identify central issues. Then a high-level process model of parallel simulation is presented to clarify essential design choices. Algorithms for parallel logic and fault simulation of synchronous gate-level designs are introduced. The algorithms are based on a partitioning approach that reduces the number of necessary synchronizations between processors. A simple performance model characterizes the dependence on some crucial parameters. Experimental results for some large benchmarks are given, using prototype implementations for both message-passing and shared-memory machines. >

CHEETA: Composition of hierarchical sequential tests using ATKET

An approach to modular and hierarchical sequential circuit test generation, which exploits a top-down design methodology, uses high level test knowledge and constraint driven module test generation to target faults at the structural level, is introduced in this paper. Results obtained for several designs are provided to demonstrate the effectiveness of our approach and the need for high level knowledge along with global constraints while deriving sequential circuit tests.<<ETX>>

Automatic test vector cultivation for sequential VLSI circuits using genetic algorithms

This paper discusses a new approach for generating test vectors, using test cultivation, for both combinational and sequential VLSI circuits described hierarchically at the transistor, gate, and higher levels. The approach is based on continuous mutation of a given input sequence and on analyzing the mutated vectors for selecting the test set. The hierarchical technique used in the analysis drastically reduces the memory requirements, allowing test generation for large circuits. The test cultivation algorithms are simulation-based and a test set can be cultivated for any circuit that can be simulated logically. In particular, general MOS digital designs can be handled, and both stuck-at and transistor faults can be accurately modeled. Using the approach, tests were generated with very high fault coverage for gate-level circuits as well as for transistor level circuits.

On the initialization of sequential circuits

A general method for determining whether a certain design is initializable, and for generating its initialization sequence, is presented. This method is based on structural decomposition of the circuit, and can handle both logical (using X-value simulation) and functional initializabilities. Results for some benchmark circuits are also presented.

Beta: behavioral testability analysis

An approach, Beta, for computing testability is presented. This approach is based on analyzing the circuits behavior description data flow graph (DFG). First, each path in the DFG is analyzed to find the set of paths to justify and propagate each data register. Then, register classification follows to diagnose every registers controllability and observability and classify them into several groups. For the most controllable and observable registers, Beta, unlike other testability methods which compute only testability, also tries to derive the exact sequence for justifying and propagating each register. Register classification is also useful in pointing out hard-to-control and hard-to-observe areas of the circuit. This approach has been implemented in a computer program and applied to several examples. These results are verified by a DFG-based test generator and proven to be successful.<<ETX>>

Automatic Generation of Instructions to Robustly Test Delay Defects in Processors

We present a technique for generating instruction sequences to test a processor functionally. We target delay defects with this technique using an ATPG engine to generate delay tests locally, a verification engine to map the tests globally, and a feedback mechanism that makes the entire procedure faster. We demonstrate nearly 96% coverage of delay faults with the instruction sequences generated. These instruction sequences can be loaded into the cache to test the processor functionally.

A massively-parallel easily-scalable satisfiability solver using reconfigurable hardware

Satisfiability (SAT) is a computationally expensive algorithm central to many CAD and test applications. In this paper, we present the architecture of a new SAT solver using reconfigurable logic. Our main contributions include new forms of massive fine-grain parallelism and structured design techniques based on iterative logic arrays that reduce compilation times from hours to a few minutes. Our architecture is easily scalable. Our results show several orders of magnitude speed-up compared with a state-of-the-art software implementation, and with a prior SAT solver using reconfigurable hardware.