Andrew W. Martwick

The repeatability of system level ESD test and relevant ESD generator parameters

Some system level ESD tests do not repeat well if different ESD generators are used. For improving the test repeatability, ESD generator specifications were considered to be changed and a world wide Round Robin test were performed in 2006 to compare the modified and unmodified ESD generators. The test results show the failure level variations up to 1:3 for an EUT among eight different ESD generators. Multiple ESD parameters including discharge currents and transient fields have been measured. This paper tries to find which parameters would predict the failure level the best in general. The transient fields show large variations among different ESD generators. The voltage induced in a semi-circular loop and the ringing after first discharge current peak show the best correlation to failure levels. The regulation on the transient field is expected to improve the test repeatability.

Silicon interposer and TSV signaling

Silicon interposers and through silicon vias are new technologies that are currently being readied for production. This research examines the electrical and timing models to predict how fast this technology will scale. We show that the metrics first introduced by W.C. Elmore to the delay and bandwidth calculations of cascaded low pass elements provide excellent predictions for the interconnect signal integrity. By applying a simple transmit equalizer we show that 6 mm links will scale to over 6 Gb/s. To support the scaling calculations we review the timing jitter model that is used to calculate the timing budget at the receiver to achieve a 0 bit error rate. This technology requires such a detailed model because the geometry is too small to allow direct measurements, it must be guaranteed by design and confirmed by margin testing.

A novel method for the analysis of ESD generators and coupling using frequency domain

A concept for analyzing ESD generators and coupling to EUTs in the frequency domain is presented. Its novelty lies in not only taking the current shaping, but also the radiation effects of structural elements and electrical components located within the ESD generator into account, without discharging the ESD generator. This is achieved by using the frequency domain and substituting the electrical breakdown within the ESD generator (contact mode) for one port of a network analyzer. The network analyzer excites all the pulse forming and the radiating elements of the ESD generator as they would be excited during a discharge. This offers the advantage of an increased dynamic range of frequency domain techniques without having to simplify the complex radiation properties of real ESD simulators. Keywords-Electrostatic Discharge; ESD, simulation, network analyzer

Pulse Edge-Only Signaling Method Comparison for Wireline Interconnects

Typical high-speed electrical transmission lines use a variety of precoding and equalization techniques to counter the frequency-dependent channel loss and environmental conditions such as ISI. In this paper, we suggest a relatively narrow-band signaling method that is resilient to the effects of ISI and crosstalk and can be implemented with existing technology. Alternative modulation schemes are analyzed in terms of effectiveness, performance, and cost. In particular, line-encoded and on-off keyed modulation methods are evaluated in simulations of transmission lines to gauge effectiveness in high-speed conditions with limiting ISI.

A Novel Method of Active Power Noise Cancellation in I/O Buffers

This paper presents a scheme to reduce the on-die voltage noise that occurs due a buffer switching event. Both output and input buffer switch events are addressed. A generic power delivery network (PDN) model with parasitic inductance is assumed. A change in current ( di/dt) across the inductor is considered the primary cause of the voltage noise. On-die decoupling capacitance is traditionally added to the power delivery network to address this problem and to limit the droop. The method described in the paper shows a principally different approach. The maximum di/dt is managed to reduce the voltage noise. It is proposed to send to a buffer a current waveform from an external supply or to recycle charge from a locally charged capacitance when the di/dt occurs, thus substantially reducing the on-die voltage noise. Alternatively, at a given acceptable level of voltage noise the on-die capacitance can be reduced, providing significantly lower product cost. This paper provides theoretical and modeling background of the proposed schemes and includes simulation results on several performance characteristics.