Jayong Koo

Susceptibility Scanning as a Failure Analysis Tool for System-Level Electrostatic Discharge (ESD) Problems

Susceptibility scanning is an increasingly adopted method for root cause analysis of system-level immunity sensitivities. It allows localizing affected nets and integrated circuits (ICs). Further, it can be used to compare the immunity of functionally identical or similar ICs or circuit boards. This paper explains the methodology as applied to electrostatic discharge and provides examples of scan maps and signals probed during immunity scanning. Limitations of present immunity analysis methods are discussed.

A Nonlinear Microcontroller Power Distribution Network Model for the Characterization of Immunity to Electrical Fast Transients

A nonlinear power distribution network model for characterizing the immunity of integrated circuits (ICs) to electrical fast transients (EFTs) is proposed and validated. The model includes electrostatic discharge (ESD) protection diodes and passive impedances between power domains. Model parameters are based on external measurements using a vector network analyzer and curve tracer. Impedance is measured between pins while the IC is biased and operating, and is used to determine individual elements of the network model. Inclusion of active power-clamp circuitry is also explored. The model is able to successfully predict pin currents and voltages during EFTs on the power pin when the IC is operating or turned off and when the ESD power clamp is either activated or not activated. This model might be used to evaluate the immunity of the IC in a variety of systems and to better understand why failures occur within the IC and how to fix them.

The repeatability of system level ESD test and relevant ESD generator parameters

Some system level ESD tests do not repeat well if different ESD generators are used. For improving the test repeatability, ESD generator specifications were considered to be changed and a world wide Round Robin test were performed in 2006 to compare the modified and unmodified ESD generators. The test results show the failure level variations up to 1:3 for an EUT among eight different ESD generators. Multiple ESD parameters including discharge currents and transient fields have been measured. This paper tries to find which parameters would predict the failure level the best in general. The transient fields show large variations among different ESD generators. The voltage induced in a semi-circular loop and the ringing after first discharge current peak show the best correlation to failure levels. The regulation on the transient field is expected to improve the test repeatability.

Modeling of the immunity of ICs to EFTs

Investigation of the immunity of ICs to EFTs is increasingly important. In this paper, an accurate model of a microcontroller is developed and verified. This model consists of two parts: a passive Power Distribution Network (PDN) model and an active I/O protection network model. Measurement methods are designed to extract the parameters of the passive PDN model. The accuracy of the overall model of the IC is verified using both S parameter tests and EFT injection tests. The model is able to accurately predict the voltage and current at power-supply and I/O pins and correctly accounts for the active components of the I/O protection network.

Modeling Injection of Electrical Fast Transients Into Power and IO Pins of ICs

A SPICE-based model of a microcontroller was developed to investigate its immunity to electrical fast transients (EFTs). The model includes representations of the on-die power delivery network, the ESD protection clamps, and the I/O driver circuits. Several measurement approaches were developed to characterize the linear and nonlinear components within the model. EFTs were injected into pins of the microcontroller to verify the accuracy of the proposed model. General purpose I/O were tested in several configurations (i.e., pull-up-enabled input, logical-high output, and logical-low output). The model was able to predict the voltage waveform and maximum voltage at each pin within 5~6% of the measured values. A parasitic bipolar junction transistor associated with the output driver was found to have a critical impact on the noise coupled to the power bus. The simplicity and accuracy of this model shows its promise for understanding and predicting immunity issues in integrated circuits.

A novel method for the analysis of ESD generators and coupling using frequency domain

A concept for analyzing ESD generators and coupling to EUTs in the frequency domain is presented. Its novelty lies in not only taking the current shaping, but also the radiation effects of structural elements and electrical components located within the ESD generator into account, without discharging the ESD generator. This is achieved by using the frequency domain and substituting the electrical breakdown within the ESD generator (contact mode) for one port of a network analyzer. The network analyzer excites all the pulse forming and the radiating elements of the ESD generator as they would be excited during a discharge. This offers the advantage of an increased dynamic range of frequency domain techniques without having to simplify the complex radiation properties of real ESD simulators. Keywords-Electrostatic Discharge; ESD, simulation, network analyzer