Andrzej Abramowski

Algorithm and Architecture Design of the H.265/HEVC Intra Encoder

Improved video coding techniques introduced in the H.265/High Efficiency Video Coding (HEVC) standard allow video encoders to achieve better compression efficiencies. On the other hand, the increased complexity requires a new design methodology able to face challenges associated with ever higher spatiotemporal resolutions. This paper presents a computationally scalable algorithm and its hardware architecture able to support intra encoding up to 2160p@30 frames/s resolution. The scalability allows a tradeoff between the throughput and the compression efficiency. In particular, the encoder is able to check a variable number of candidate modes. The rate estimation based on bin counting and the distortion estimation in the transform domain simplify the rate-distortion analysis and enable the evaluation of a great number of candidate intra modes. The encoder preselects candidate modes by the processing of 8 × 8 predictions computed from original samples. The preselection shares hardware resources used for the processing of predictions generated from reconstructed samples. To support intra 4×4 modes for the 2160p@30 frames/s resolution, the encoder incorporates a separate reconstruction loop. The processing of blocks with different sizes is interleaved to compensate for the delay of reconstruction loops. Implementation results show that the encoder utilizes 1086k gates and 52-kB on-chip memories for TSMC 90 nm. The main reconstruction loop can operate at 400 MHz, whereas the remaining modules work at 200 MHz. For 2160p@30 frames/s videos, the average BD-rate is 5.46% compared with that of the HM software.

A Novel Intra Prediction Architecture for the Hardware HEVC Encoder

This work presents a novel Intra prediction architecture for the hardware High Efficiency Video Coding (HEVC) encoder. The architecture supports full range of features included in the standard, in accordance with the Main and Main 10 profiles, i.e. all modes and all Prediction Unit (PU) sizes. The architecture embeds the internal RAM working at the doubled clock rate to provide quick access to reference samples. This also leads to a reduction of required number of registers, while maintaining a high throughput. All needed multiplications are carried out using multiplexers and adders. The module provides a few soft configuration options, allowing the encoder to skip some modes and PU sizes. This feature trades computation time for compression efficiency. The module can produce 8x8 prediction blocks almost in each clock cycle. The design can operate at 100 MHz and 200 MHz for FPGA Aria II devices and the TSMC 0.13μm technology, respectively. The implementations generating all allowable predictions are able to process almost 15 and 30 frames per second for 1080p sequences for FPGA and ASIC, respectively. When 4x4 predictions are off, the trough put is doubled.

A double-path intra prediction architecture for the hardware H.265/HEVC encoder

This paper presents an innovatory approach to the design of the intra prediction architecture for the hardware H.265/HEVC (High Efficiency Video Coding) encoder. As the most of the computational complexity in the intra prediction algorithm is associated with the need to process number of 4×4 Prediction Units (PUs), an independent processing path is proposed for this specific PU size with a separate reconstruction loop. The final result from this path is then incorporated into the second path, independently checking all the remaining PUs. This approach does not entail a significant increase in utilization of hardware resources, while considerably accelerates the encoding. The proposed architecture can operate at 100 MHz for FPGA Aria II devices and at 200 MHz for the TSMC 0.13μm technology. The achieved throughput allows the processing of almost 17.5 and 35 1080p frames per second using FPGA and ASIC technology, respectively. The solution is compliant with the Main, Main 10, and Main Still Picture profiles of the H.265/HEVC standard.

Towards H.265 video coding standard

This document presents a short description of the current stage of works on H.265/HEVC video coding standard, which is being prepared by the JCT-VC group in order to achieve a 50% reduction of the data rate needed for high quality video coding, as compared to the current H.264/AVC standard. The gain should be achieved by an inclusion of a few new coding techniques and improvements to each step of original H.264/AVC coding algorithm. The proposed changes also ought to broaden the range of possible standard applications.

Implementation of multistandard video signals integrator

The paper describes the prototype implemetantion of the Video Signals Integrator (VSI). The function of the system is to integrate video signals from many sources. The VSI is a complex hybrid system consisting of hardware, firmware and software components. Its creation requires joint effort of experts from different areas. The VSI capture device is a portable hardware device responsible for capturing of video signals from different different sources and in various formats, and for transmitting them to the server. The NVR server aggregates video and control streams coming from different sources and multiplexes them into logical channels with each channel representing a single source. From there each channel can be distributed further to the end clients (consoles) for live display via a number of RTSP servers. The end client can, at the same time, inject control messages into a given channel to control movement of a CCTV camera.

Video signals integrator (VSI) system architecture

The purpose of the project is development of a platform which integrates video signals from many sources. The signals can be sourced by existing analogue CCTV surveillance installations, recent internet-protocol (IP) cameras or single cameras of any type. The system will consist of portable devices that provide conversion, encoding, transmission and archiving. The sharing subsystem will use distributed file system and also user console which provides simultaneous access to any of video streams in real time. The system is fully modular so its extension is possible, both from hardware and software side. Due to standard modular technology used, partial technology modernization is also possible during a long exploitation period.

A survey over possible intra prediction optimizations in the H.265/HEVC encoder

The H.265/HEVC standard is state-of-the-art solution in the field of video compression. It utilizes various techniques to maximize achieved compression efficiency, including quad-tree syntax organization and powerful prediction algorithms. The quad-tree approach allows the flexible adaptation to various texture characteristics at the expense of the dramatic increase in computational complexity. This results in very long encoding times, especially while using the reference software, known as HM. However, over the years, miscellaneous heuristics were developed to accelerate the selection of the optimal CTU division and the prediction mode. This paper is an overview of the most promising heuristics, designed for intra frames.

Performance evaluation of the intra compression in the video coding standards

The article presents a comparison of the Intra prediction algorithms in the current state-of-the-art video coding standards, including MJPEG 2000, VP8, VP9, H.264/AVC and H.265/HEVC. The effectiveness of techniques employed by each standard is evaluated in terms of compression efficiency and average encoding time. The compression efficiency is measured using BD-PSNR and BD-RATE metrics with H.265/HEVC results as an anchor. Tests are performed on a set of video sequences, composed of sequences gathered by Joint Collaborative Team on Video Coding during the development of the H.265/HEVC standard and 4K sequences provided by Ultra Video Group. According to results, H.265/HEVC provides significant bit-rate savings at the expense of computational complexity, while VP9 may be regarded as a compromise between the efficiency and required encoding time.

Hardware-oriented simplifications of the prediction algorithms in the H.265/HEVC encoder

This paper presents a hardware-oriented analysis of the mode decision algorithms for intra and inter prediction in the H.265/HEVC encoder. A number of simplifications, aimed to achieve real-time encoding of high-resolution video sequences in the hardware implementation, is proposed. The potential acceleration of the encoding is associated with losses in the encoding efficiency. Therefore, the trade-off between encoding speed and quality is inspected closely.

An FPGA architecture for MPEG-2 TS demultiplexer

This paper presents a novel architecture of a MPEG-2 TS demultiplexer, implemented with a FPGA. The main objective of the design is an ability to separate selected elementary streams in real time, while ensuring minimal resource consumption. This is achieved by the decomposition of the demultiplexer into a number of independent sub-modules, which process the data in parallel. The flexible structure enables adaptation to the specific needs and significantly simplifies potential expansion, what may be important due to a wide range of potential applications of the MPEG-2 TS standard. To improve the functionality, the demultiplexer is equipped with a configuration and status interface. The transport stream and configuration data are supplied to the FPGA by a microcontroller through the External Peripheral Interface (EPI). The data is transmitted to the microcontroller via Ethernet, using the User Datagram Protocol (UDP).