Andrzej Peczalski

Analysis of noise margin and speed of GaAs MESFET DCFL using UM-SPICE

Using a customized GaAs IC circuit simulator (UM-SPICE) the design trade-offs and process sensitivity of the logic levels, noise margin, and propagation delay for GaAs direct coupled field effect logic (DCFL) gates are analyzed. The results of the circuit simulation are shown to be in good agreement with our experimental data. For DCFL gates with ungated FET loads studied here, the noise margin is found to be the more important design criteria. The noise margin is a sensitive function of both the driver-to-load current ratio and the driver threshold voltage, whereas the propagation delay remains fairly constant over a wide range of driver-to-load ratios and threshold voltages. Our simulations indicate that a driver-to-load ratio of about 5 and a threshold voltage of about 0.1 V would offer the optimum performance for most applications. Also, the DCFL design with shallow channel transistor appears to be less sensitive to the substrate or implantation variations.

Electron mobility and velocity in compensated GaAs

We present the results of a Monte Carlo calculation of the electron velocity and mobility, as well as mobility measurements in compensated GaAs. For appreciable compensation ratios, the peak velocity, negative differential mobility, and peak‐to‐valley velocity ratios are drastically reduced in comparison with those in uncompensated GaAs. This reduction makes the Gunn effect less likely to manifest itself in ion‐implanted GaAs metal‐semiconductor field‐effect transistors and other GaAs devices where compensation is important.

Subthreshold current ion GaAs MESFETs

The authors present experimental data that show that the drain-to-source voltage dependence of the subthreshold current in GaAs MESFETs is determined by the variation of threshold voltage with drain-source voltage and not by Schottky-barrier lowering. This model, incorporating gate-to-drain and gate-to-source diode currents, is shown to be in good agreement with measured data. The model is incorporated into a GaAs circuit simulator and is suitable for GaAs IC design.<<ETX>>

Modeling frequency dependence of GaAs MESFET characteristics

We present a new method of modeling the output conductance dispersion of GaAs MESFETs. High frequency model parameters are extracted and then used to model high frequency output conductance over a wide range of bias conditions. The model is then used to simulate and analyze the effect of output conductance dispersion on the performance of DCFL and SCFL logic gates. Whereas the DCFL performance is not significantly affected by the high frequency effects, the noise margin of SCFL decreases by almost a factor of 30% above 100 kHz, with an associated decrease in the voltage swing and gate delay. >

Monte Carlo studies of electronic transport in compensated InP

The steady‐state velocity‐field characteristics for n‐type InP are obtained via a Monte Carlo calculation for temperatures between 77 and 400 K, as well as for impurity compensation ratios between 0.0 and 0.9. Electron drift mobilities, peak velocities, and peak electric fields are extracted by a curve fitting procedure. A comparison with reported GaAs values suggests that InP has some superior transport characteristics and is well suited for high‐frequency/gain electronic device applications. This improvement was seen to be due mainly to high L‐Γ and X‐Γ energy valley separations in InP. An empirical relationship between drift velocity and applied electric field, with the low‐field drift mobility as an input parameter is presented for use in computer modeling of InP devices.

The performance of source-coupled FET logic circuits that use GaAs MESFETs

Gallium arsenide (GaAs) source-coupled FET logic (SCFL) circuits have demonstrated a wide range of tolerance to threshold voltage and a partial immunity to temperature variation. A complete SCFL implementation including the voltage reference circuit for both high-speed and low-power applications is described. >

Design Analysis of GaAs Direct Coupled Field Effect Transistor Logic

Parameters of a DCFL inverter, such as propagation delay, inverter gain, switching voltage, output voltage levels and noise margins, are related (in an analytical form) to the parameters of the switching transistor and load transistor, such as the load saturation current, the switching transistor threshold voltage, the load and switching transistor output conductances, etc., and to the gate fan-in and fan-out. The results demonstrate tradeoffs between the noise margins, propagation delay and power consumption and are in reasonable agreement with experimental data for GaAs self-aligned inverters and with the results of circuit simulation of DCFL inverters and ring oscillators.

Modeling and characterization of ion-implanted GaAs MESFET's

Accurate modeling of GaAs ICs requires a good fit to the device characteristics over the entire range of gate and drain voltages. However, the existing circuit simulator models suitable for circuit simulation fail in the linear region of the current-voltage characteristics. In this paper, we demonstrate that the nonuniformity of the mobility and doping profiles strongly affects the linear region and propose an analytical model taking this nonuniformity into account. We also present the characterization techniques that relate the model parameters to the device physics and the fabrication methods. Excellent agreement with experimental data is obtained and the model is implemented into our GaAs IC circuit simulator.

Monte Carlo studies of steady‐state electronic transport in compensated In0.53Ga0.47As

The steady‐state velocity‐field characteristics of n‐type In0.53Ga0.47As are obtained through a Monte Carlo calculation for temperatures between 77 and 400 K, and for compensation ratios Na/Nd between 0 and 0.9. Alloy scattering is found to play a significant role in the low‐temperature regime. Low‐field electron drift mobilities are extracted from the velocity‐field curves. We conclude by suggesting empirical relationships which model the velocity‐field characteristics as a function of low‐field electron drift mobility.

Low-power 2K-cell SDFL gate array and DCFL circuits using GaAs self-aligned E/D MESFETs

Using GaAs self-aligned gate MESFETs, low-power logic circuits have been demonstrated for both depletion-mode (D-mode) Schottky-diode FET logic (SDFL) and enhancement/depletion-mode (E/D-mode) direct-coupled FET logic (DCFL). Propagation delays of 1.6 ns have been obtained for SDFL operating are 108 mu W per gate. DCFL has demonstrated ring-oscillator gate delays of 30 ps and speed-power products as low as 1.1 fJ per gate. A 2K-cell gate array designed with low-power SDFL has demonstrated an 8-bit adder with an add time of 11 ns at 236 mW. Automatic software was used for the placement and routine of the 8-bit adder in the gate array. DCFL divide-by-four circuits designed for 500-MHz operation have demonstrated up to 2.5-GHz operation with a power dissipation of 172 mu W per gate at 1-GHz clock frequency. DCFL divide-by-four circuits subjected to 3.4*10/sup 7/ rads (Si) and 1*10/sup 14/ N/cm/sup 2/, for total dose and neutron fluence, respectively, have demonstrated only minimal reduction in power and no degradation of circuit performance. >