Kang W. Lee

Current—Voltage characteristics of ungated GaAs FET's

We develop a model which describes the current-voltage characteristics of GaAs saturated resistor loads (or ungated FETs) with uniform and nonuniform (ion-implanted) doping profiles. The results of the calculation are in good agreement with the experimental data for 1-, 2-, and 3-µm GaAs ungated FETs. Our model allows us to determine the values of the electron saturation velocity νsand of the surface built-in voltage VSbifrom the measured current-voltage characteristics of ungated loads. For long devices (with 3-µm length) we obtain\nu_{s} \approx 1.20-1.21 \times 10^{5}m/s andV_{Sbi} \approx 0.46-0.47V, in good agreement with expected values. For shorter (1 µm) devices, the measured values of νsare considerably higher (1.64-1.73 × 105m/s). This may be considered as evidence of velocity enhancement in short structures due to ballistic or overshoot effects.

FET Characterization using gated-TLM structure

A new FET characterization structure consisting of parallel ohmic contacts with gates of varying lengths in between is described. The FET source resistance is accurately measured without parameter fitting or iteration. The low-field electron mobility beneath the gate is determined as an effective uniform value and as a function of distance into the channel without iteration. The use of this structure is demonstrated on self-aligned ion-implanted GaAs MESFETs.

A gallium arsenide SDFL gate array with on-chip RAM

A GaAs gate array has been fabricated featuring 432 SDFL cells, 32 interface I/O buffer cells, and four 4 × 4 bit static RAMs. Each Schottky diode field-effect transistor logic (SDFL) cell can be programmed with 3 options as an unbuffered or buffered NOR gate, or as a dual OR/NAND gate. The interface I/O cell can be programmed for ECL, TTL, CMOS, and SDFL logic families. Each 16 bit RAM is fully decoded using depletion mode MESFETs with SDFL circuit approach. The chip size is 147 mils × 185 mils, and the total power dissipation of the whole chip is less than 3 W. Testing of the cell array has given yields of 70 percent for the 101-stage ring oscillators and about 90 percent for the I/O buffers, memory cells, and 25-stage ring oscillators in a wafer. The best speed performance of the unbuffered SDFL gate is 150 ps for fan-out and fan-in of 1 and the load of 100 µm of interconnect. The average power of the SDFL gate is 1.5 mW. The results demonstrated the feasibility of the GaAs SDFL for fast gate array and memory applications.

The performance of source-coupled FET logic circuits that use GaAs MESFETs

Gallium arsenide (GaAs) source-coupled FET logic (SCFL) circuits have demonstrated a wide range of tolerance to threshold voltage and a partial immunity to temperature variation. A complete SCFL implementation including the voltage reference circuit for both high-speed and low-power applications is described. >

Design Analysis of GaAs Direct Coupled Field Effect Transistor Logic

Parameters of a DCFL inverter, such as propagation delay, inverter gain, switching voltage, output voltage levels and noise margins, are related (in an analytical form) to the parameters of the switching transistor and load transistor, such as the load saturation current, the switching transistor threshold voltage, the load and switching transistor output conductances, etc., and to the gate fan-in and fan-out. The results demonstrate tradeoffs between the noise margins, propagation delay and power consumption and are in reasonable agreement with experimental data for GaAs self-aligned inverters and with the results of circuit simulation of DCFL inverters and ring oscillators.

Low-power 2K-cell SDFL gate array and DCFL circuits using GaAs self-aligned E/D MESFETs

Using GaAs self-aligned gate MESFETs, low-power logic circuits have been demonstrated for both depletion-mode (D-mode) Schottky-diode FET logic (SDFL) and enhancement/depletion-mode (E/D-mode) direct-coupled FET logic (DCFL). Propagation delays of 1.6 ns have been obtained for SDFL operating are 108 mu W per gate. DCFL has demonstrated ring-oscillator gate delays of 30 ps and speed-power products as low as 1.1 fJ per gate. A 2K-cell gate array designed with low-power SDFL has demonstrated an 8-bit adder with an add time of 11 ns at 236 mW. Automatic software was used for the placement and routine of the 8-bit adder in the gate array. DCFL divide-by-four circuits designed for 500-MHz operation have demonstrated up to 2.5-GHz operation with a power dissipation of 172 mu W per gate at 1-GHz clock frequency. DCFL divide-by-four circuits subjected to 3.4*10/sup 7/ rads (Si) and 1*10/sup 14/ N/cm/sup 2/, for total dose and neutron fluence, respectively, have demonstrated only minimal reduction in power and no degradation of circuit performance. >

Multiple-input and -output OR/AND circuits for VLSI GaAs IC's

OR/AND circuits with multiple input and output have been demonstrated experimentally for low-power 2K and 6K GaAs gate arrays with two levels of logic at approximately a 155-percent increase in speed and power product. The proposed multiple-logic levels process in parallel some complex logic functions with only one gate delay. Two proposed bootstrap techniques have shown an improvement of typically 12 percent in speed without an increase in power for low-power applications. In coupling these OR/AND circuits with the allowable buffered stage and the bootstrap enhancements, one can obtain good device performance over a spectrum of SSI to VLSI in the SDFL circuit family.