Andrzej Pfitzner

Stacked 3-dimensional 6T SRAM cell with independent double gate transistors

A stacked three-dimensional six transistor SRAM cell using a novel vertical slit field effect transistor with two independently controlled gates is proposed. A compact stacked 3D memory cell topology with a highly regular layout is presented and a significant memory cell area reduction can be achieved. Utilization of independent double gate transistors enhances the robustness for read and write operation. The trade-off for the use of independently controlled gates to increase the cell stability is discussed.

Realizing and and or Functions With Single Vertical-Slit Field-Effect Transistor

This letter experimentally demonstrates and and or functionalities with a single MOS transistor. Device architecture and fabrication follow the recent work on fabrication-based feasibility assessment of junctionless vertical-slit field-effect transistor. Slit width variation is used to realize a particular functionality-wider for or function and narrower for and function. The fabricated n-type devices with the and and or functionalities exhibit good electrical performance: low off current (<; 5 pA/μm) and high ION/IOFF ratio (>; 106). Furthermore, we briefly discuss the implication of these devices in CMOS NAND logic implementation.

Is there always performance overhead for regular fabric

In this paper, we study the circuits built from super-regular, high-density transistor arrays that can be prefabricated and customized using an OPC-free interconnect manufacturing process. The super-regular layout style greatly enhances the chippsilas manufacturability. Unlike other regular fabrics that sacrifice area and performance to improve regularity, the new layout style, combined with a new 3-D geometry transistor, enables to produce circuits with timing and power density comparable to or better than that of conventional CMOS circuits and using less chip area.

Adder circuits with transistors using independently controlled gates

Circuits with transistors using independently controlled gates have been proposed to reduce the number of transistors and to increase the logic density per area. So far only small building blocks have been presented. This paper investigates for the first time the use of independent double gate transistors in 16 bit ripple carry and parallel prefix adders. New adder circuits and the trade-off between area reduction, delay and power consumption are presented. Area and transistor count reduction by one third can be achieved.

Static Power Consumption in Nano-CMOS Circuits: Physics and Modelling

Static power consumption due to excessive leakage currents is a major problem in CMOS digital ICs with gate lengths of 90 nm and below. In this paper the physics and modelling of these currents is discussed, with special emphasis on variability and its effect on the statistical spread of the static power consumption and total power consumption.

Neighbourhood problem in interconnection capacitance modeling

Modern VLSI circuits become more and more complex. For simulation purposes (especially statistical simulation) simple but precise analytical models of interconnection capacitances are necessary. Existing models take into account only the closest neighbourhood of the line. This paper presents example results of simulations showing that number of the parallel lines taken into account influences accuracy of signal delay and crosstalk evaluation.

Improved simple DC model of Vertical-Slit Field-Effect Transistor (VeSFET)

In this paper a simple compact DC model of junction-less twin-gate Vertical-Slit Field-Effect Transistor (VeSFET) has been developed*. This device is the elementary component of a new 3D VeSTIC technology [1]. Feasibility studies conducted until now, confirm the attractive electrical properties of VeSFETs and indicate that VeSTIC architecture has the potential to overcome many barriers of ICs scaling in the deep-submicron era. The first, rudimentary compact DC model provided in [5] combined physical description with empirical formulas. That model has been improved here to considerably reduce the number of fitting parameters, retaining high accuracy. Good universality of the model was verified for various geometric and material parameters of the VeSFET structure.

Interconnection Capacitances Dependence On Further Neighbourhood In The Bus - Experimental Verification Of The Model

An analytical model, taking into account the further neighbourhood influence on interconnection capacitances was proposed in our previous works (Jarosz, 2002). In this paper a method of experimental verification of those formulas and a test chip designed for the AMS 0.35mum technology are presented. Results of measurements and the correctness of the model are discussed

Usefulness of VeSTIC devices for low-noise and radiation hard 3D integrated circuits

VeSTIC technology [1, 2] is a very promising concept of digital, analog and mixed mode ICs design, providing very large scale of integration, extreme layout regularity, as well as the possibility of manufacturing cost reduction and of fully three-dimensional integration. These features seem to be very attractive also in the case of MEMS systems, in particular MAP sensors. With regard to prospective applications, a first insight to noise spectra and radiation hardness of the field-effect VeSTIC devices has been performed and confirms their usefulness.

Vertical Slit Transistor based Integrated Circuits (VeSTICs)

Vertical slit 3D device architecture, proposed by W. Maly, can be shared by a variety of different types of transistors including a new junctionless N-channel and P-channel vertical slit FET (VeSFET). VeSFETs have two symmetrical independent gates that provide many new circuit level opportunities e.g. in energy conservation domain, unavailable otherwise. The key feature of the new architecture is its extreme regularity, which promotes highly repetitive layouts, constructed with small number of massively replicated simple geometrical patterns vastly simplifying critical lithography steps. A single layer of VeSFETs is a canvas for Vertical Slit Transistor based Integrated Circuits (VeSTICs). Proposed new IC design/manufacturing paradigm can deliver high manufacturing efficiency (as has been achieved by memory producers) combined with fast and inexpensive design.