Dominik Kasprowicz

Stacked 3-dimensional 6T SRAM cell with independent double gate transistors

A stacked three-dimensional six transistor SRAM cell using a novel vertical slit field effect transistor with two independently controlled gates is proposed. A compact stacked 3D memory cell topology with a highly regular layout is presented and a significant memory cell area reduction can be achieved. Utilization of independent double gate transistors enhances the robustness for read and write operation. The trade-off for the use of independently controlled gates to increase the cell stability is discussed.

Realizing and and or Functions With Single Vertical-Slit Field-Effect Transistor

This letter experimentally demonstrates and and or functionalities with a single MOS transistor. Device architecture and fabrication follow the recent work on fabrication-based feasibility assessment of junctionless vertical-slit field-effect transistor. Slit width variation is used to realize a particular functionality-wider for or function and narrower for and function. The fabricated n-type devices with the and and or functionalities exhibit good electrical performance: low off current (<; 5 pA/μm) and high ION/IOFF ratio (>; 106). Furthermore, we briefly discuss the implication of these devices in CMOS NAND logic implementation.

Is there always performance overhead for regular fabric

In this paper, we study the circuits built from super-regular, high-density transistor arrays that can be prefabricated and customized using an OPC-free interconnect manufacturing process. The super-regular layout style greatly enhances the chippsilas manufacturability. Unlike other regular fabrics that sacrifice area and performance to improve regularity, the new layout style, combined with a new 3-D geometry transistor, enables to produce circuits with timing and power density comparable to or better than that of conventional CMOS circuits and using less chip area.

Adder circuits with transistors using independently controlled gates

Circuits with transistors using independently controlled gates have been proposed to reduce the number of transistors and to increase the logic density per area. So far only small building blocks have been presented. This paper investigates for the first time the use of independent double gate transistors in 16 bit ripple carry and parallel prefix adders. New adder circuits and the trade-off between area reduction, delay and power consumption are presented. Area and transistor count reduction by one third can be achieved.

Static Power Consumption in Nano-CMOS Circuits: Physics and Modelling

Static power consumption due to excessive leakage currents is a major problem in CMOS digital ICs with gate lengths of 90 nm and below. In this paper the physics and modelling of these currents is discussed, with special emphasis on variability and its effect on the statistical spread of the static power consumption and total power consumption.

Improvement of integrated circuit testing reliability by using the defect based approach

Abstract The systematic decrease in the minimum feature size in VLSI circuits makes spot defects an increasingly significant cause of ICs’ faults. A testing method optimized for detecting faults of this origin has been recently developed. This method, called defect based testing (DBT), requires a lot of computational effort at the stage of testing-procedure preparation, which makes it appear less attractive than the well-known stuck-at-fault oriented testing. This paper, however, shows that a stuck-at-fault-optimized test-vector set may prove highly inefficient in detecting spot-defect-induced faults. Experiments with the C17 ISCAS-85 testability benchmark show that the risk of a spot-defect damaged circuit passing the test is dangerously high if the test set was designed with stuck-at-faults in mind. It is also shown that although spot defects may in some cases transform a combinational circuit into a sequential one, in practice this phenomenon does not require any special treatment from the test designer. Eventually, a few methods are discussed that make the DBT less time consuming.

Small-signal lumped-element equivalent model for high operating temperature infrared photodetectors

We present a simple small-signal parameterized equivalent circuit for HgCdTe photodetectors operating at high temperatures in the middle and long wavelength of the infrared spectrum. This circuit is capable of accurate modeling the impedance of these devices upon bandwidth of several GHz and for a wide range of bias voltage and temperatures. We have implemented this model as a parameterized sub-circuit in generic circuit simulator from SPICE family, to study conditions for signal propagation in the photodetector signal path at low level of IR illumination. Analyses based on this model provide a useful insight into photodiode operation.

VeSFET as an analog-circuit component

The Vertical Slit-based Field-Effect Transistor (VeSFET) is a novel junctionless device with two identical, independently controlled gates. The VeSFET, so far prototyped only as single-device test structures, has been considered in the literature exclusively as a component of digital systems. This paper shows that the devices properties make it attractive also for the analog designer. Some of the VeSFETs analog-design related parameters are compared with those of the MOSFET of the corresponding technology node. Subsequently, a two-stage Miller operational transconductance amplifier (OTA) is proposed that makes use of the VeSFETs two independently-controlled gates to drastically reduce the common-mode gain. An example application of the OTA in a current mirror is also presented.

Variability-aware table-based DC model of a dual-gate transistor

This paper presents a variability-aware table-based model of a transistor. It is shown to accurately capture its transfer curves in the presence of multiple geometry variations. The model has been successfully applied to the VeSFET — a transistor with two independent gates.

Channel charge model of a dual-gate junctionless transistor

This paper presents a semi-empirical model of the mobile charge in the channel of a junctionless dual-gate MOSFET. Its accuracy has been demonstrated to be better than 1% of the total depletion charge for a wide range of channel thickness and substrate doping values.