Andrzej Pulka

Polish semantic speech recognition expert system supporting electronic design system

The paper presents an EDA system, which is supported by the experimental speech recognition system menu with the dialog module. The main idea of the system is presented. Some aspects concerning the proposed speech recognition methodology are described. Problems specific to the Polish language are emphasized. The idea of dialog system menus is discussed. The inference engine based on AI techniques supporting Polish (natural) language processing is proposed. The entire expert system architecture is introduced. Implementation and examples are discussed.

VEST - An intelligent tool for timing SoCs verification using UML timing diagrams

The paper concerns problems of the formal verification of timings in complex electronic devices - systems on chip (SoC). The authors discuss various approaches to complex systems verification. The formal procedures for systems timings checking are presented. The models are defined as models of computation in the heterogeneous (HDL/SystemC/MATLAB) environment. The verification process is performed on intermediate UML descriptions. The methodology makes use of timing diagrams introduced to UML 2.x standard. The entire system works under VEST (verification expert system tool) implemented in PROLOG. Some experiments and results concerning communication within AMBA-bus based platform are considered.

Modeling Assistant — A Flexible VCM Generator in VHDL

In this chapter the Modeling Assistant (MA) — an environment for automated generation of VHDL models of complex digital devices — is shown. The presented system is based on the VITAL Models Generator, an automated standard components generator supplied with AI tools [Pulk97]. Additionally the proposed system contains the library of templates (VITAL library of components).

On FPGA dedicated SFC synthesis and implementation according to IEC61131

The paper presents the synthesis and implementation algorithms of reconfigurable logic controller (RLC) implemented in a FPGA. In opposite to software centric PLCs, the RLC utilize massively parallel hardware execution of control algorithms. The specific hardware implementation significantly reduces the throughput time. The input program is described by the SFC given according to IEC61131-3 standard. An original intermediate representation with use of data flow graph has been developed for program representation and synthesis purposes. The algorithm of creating graph representation maintains sequential dependencies of processing and reveals parallel tasks. Developed method of scheduling and mapping is dedicated for implementation in LUT based FPGA devices. There are considered direct mapping based on greedy approach and optimized methods that are FPGA architecture aware. The paper is concluded with exemplary implementation comparison.

Dynamic rescheduling of tasks in time predictable embedded systems

The work concerns an approach to the multi-threading and multitasking problem. The main research objective of the time predictable real-time systems is identified. A brief summary of the related works is given. Idea of thread interleaving is described and the architecture of the proposed time predictable embedded system is presented. The solution of the dynamic interleave controller of threads (DICT) with dynamically modified (reconfigured) priorities of tasks (threads) is analyzed. The paper investigates the model of the system and gives its simulation results. The entire system is synthesized in the hardware structure. Some experiments with that emphasize advantages of the proposed hardware implementation.

A new hardware algorithm for searching genome patterns

The paper deals with a very hot problem concerning computation biology - the searching for a given reference pattern within a very long DNA chain. The software solutions in the field are limited by amount of resources and processing times. That is why complex programmable devices are more and more commonly used in the applications concerning microbiology. The paper presents the approach which is a modified Smith-Waterman dynamic programming methodology. The optimization of the entire algorithm and used resources has been done with respect of properties of FPGA components.

SystemC models generation based on libraries of templates

The work concerns one of the most important problems in the field of design, modeling and simulation of modern electronic embedded systems at a very high level of abstraction - i.e. system level modeling. The approach to modeling of SoC in SystemC (2003) is presented. The author formulates philosophy of the PROLOG expert system that aids the process of models generation. Main assumptions of the library of templates and knowledge representation are given. The SMOG algorithm is described and finally the system platform and some examples are discussed

A heterogenous approach to symbolic calculations based on structural numbers

The paper presents an approach to the problem of automated generation of symbolic functions for complex electronic circuits. The new methodology based on structural numbers combined with graph theory is described. The algorithm is formulated and its implementation as BASE program is presented on examples. Results presenting generation times are given. Comparison to classical techniques and benefits of new approach summarize the contribution.

Multithread RISC architecture based on programmable interleaved pipelining

The paper deals with problems of design of complex electronic devices with predictable timing. The original solution of multithread interleaved pipelined architecture with programmable length of threads is proposed. The appropriate HDL models of main core (RISC based processor) and interleave controller are discussed. The experiments presenting problem of priorities, time length of threads, deadlines control, switching between threads, and control of the access to the memory are analyzed and discussed.

Complex mathematical models simulation on mixed HDL-simulink platform

The paper concerns the problem of verification of the complex abstract models in the simulation environment. The models with huge number of computation efforts have been considered. We have pointed out that simulation of such models in dasiapure HDLpsila is very difficult and costly; it requires from designer many additional skills and is time-consuming. Instead, we have proposed an alternative approach based on mixed HDL-Simulink platform. Basic properties of the simulation process in Simulink are addressed. The problems of data and signal transfers, driving samples, synchronization and entire communication between HDL and Simulink are described in details. Some simulation examples and conclusions concerning the methodology are presented.