Adam Milik

Logic synthesis based on decomposition for CPLDs

The paper presents a decomposition method dedicated for PAL based CPLDs. Non-standard usage of decomposition, which leads to the minimization of area in an implemented circuit and the reduction of used logic blocks in a programmable structure, is the aim of the proposed method. Each decomposition step (bound set selection, graph colouring, column pattern coding, etc.) is oriented for implementation in a PAL-based structure that is characterized by a PAL-based logic block. The proposed decomposition method is an extension of the classical approach, commonly thought to be adequately efficient. Experiments carried out on typical benchmarks show significant area reduction.

Central Processing Units for PLC implementation in Virtex-4 FPGA

Abstract The paper presents an approach to the design and construction of central processing units for programmable logic controllers implemented in a FPGA development platform. Presented units are optimised for minimum response- and throughput time. The CPU structure is based on bit-word architecture and two types of control data exchange methods: with handshaking – control data are passed through the two flip-flop units with acknowledgement; without handshaking – control data are passed through the dual port RAM. Third unit – simple one processor – built to compare with the above two. The paper presents specific timers/counters hardware construction solution. Additionally it presents implementation results which show how many FPGA circuit resources are used to implement presented units.

High level synthesis - reconfigurable hardware implementation of programmable logic controller

Abstract The paper presents implementation of PLC (hardware and software part) with use of reconfigurable logic devices (based on FPGAs). Different framework architectures that accommodate user requirements are presented. There is widely discussed synthesis process of control algorithm given by LAD. The synthesis process is targeted for hardware implementation in FPGA structure. Different optimization aspects and architecture optimal fitting are presented. Finally benchmarks compare logic requirements for controller and its performance in comparison to standard industrial solution.

A novel method of two-stage decomposition dedicated for PAL-based CPLDs

A PAL-based logic block is the core of great majority of contemporary CPLD devices. The purpose of the paper is to present a novel method of two-stage PAL decomposition. The idea of the method consist in sequential search for a decomposition providing feasibility of implementation of the free block in a PAL-based logic block containing a limited number of product terms. The proposed approach is an alternative to the classical method based on two-level minimization of separate single-output functions. Results of experiments, which are also presented, prove that the proposed algorithm leads to significant reduction of chip area in relation to the classical method, especially for CPLD structures consisting of PAL-based logic blocks containing 2/sup i/ (a power of 2) product terms.

On hardware synthesis and implementation of PLC programs in FPGAs

Many processes require controllers with an instant response (e.g. motor control, CNC machines). A high-performance PLC can be constructed with use of programmable logic devices. A lack of custom synthesis tools disables the use of standard languages widely accepted by automation designers. The paper presents the systematic process of a PLC program synthesis to hardware structure. An input PLC program is given according to the IEC61131-3 standard. The synthesis process has been developed for implementation of a program described with the LD and SFC languages. The essential idea of synthesis process is obtaining a massively parallel operating hardware structure that significantly reduces response processing time. The PLC program is translated into originally developed dedicated graph structure that enables a wide range of optimizations. In the next step, it is mapped into a hardware structure. In order to reduce resource requirements, a strategy with resource sharing is shown, which is an original extension of general mapping concepts. Modern FPGAs are equipped with arithmetic cores dedicated for signal processing, inspiring the development of the original DSP48 block mapping strategy. It attempts to utilize all features of the block in the pipelined calculation model. The considerations are summarized with the implementation result compared against standard PLC implementation, a mutual comparison of general hardware mapping, and with the use of DSP48 units.

VEST - An intelligent tool for timing SoCs verification using UML timing diagrams

The paper concerns problems of the formal verification of timings in complex electronic devices - systems on chip (SoC). The authors discuss various approaches to complex systems verification. The formal procedures for systems timings checking are presented. The models are defined as models of computation in the heterogeneous (HDL/SystemC/MATLAB) environment. The verification process is performed on intermediate UML descriptions. The methodology makes use of timing diagrams introduced to UML 2.x standard. The entire system works under VEST (verification expert system tool) implemented in PROLOG. Some experiments and results concerning communication within AMBA-bus based platform are considered.

PID Module for Reconfigurable Logic Controller

Abstract The paper presents a module of PID controller builds in FPGA structure of Reconfigurable Logic Controller. It presents algorithms used to built the controller and implementation process. Implementation process shows the ways of minimising the controller structure and increasing it performance in FPGA structures. Finally it discuses achieved result.

Decomposition of multi-output functions for CPLDs

A paper presents decomposition method dedicated for PAL based CPLDs. Non-standard usage of decomposition, that leads to minimization of area in implemented circuit and reduction of used logic blocks in programmable structure is the aim of proposed method. Each decomposition step (bound set selection, graph colouring, column pattern coding, etc) is oriented for implementation in PAL-based structure that characterized by PAL-based logic block. Proposed decomposition method is an extension of classical approach commonly thought to be sufficiently efficient. Experiments that were carried out on typical benchmarks show significant area reduction.

On FPGA dedicated SFC synthesis and implementation according to IEC61131

The paper presents the synthesis and implementation algorithms of reconfigurable logic controller (RLC) implemented in a FPGA. In opposite to software centric PLCs, the RLC utilize massively parallel hardware execution of control algorithms. The specific hardware implementation significantly reduces the throughput time. The input program is described by the SFC given according to IEC61131-3 standard. An original intermediate representation with use of data flow graph has been developed for program representation and synthesis purposes. The algorithm of creating graph representation maintains sequential dependencies of processing and reveals parallel tasks. Developed method of scheduling and mapping is dedicated for implementation in LUT based FPGA devices. There are considered direct mapping based on greedy approach and optimized methods that are FPGA architecture aware. The paper is concluded with exemplary implementation comparison.

On Translation of LD, IL and SFC Given According to IEC-61131 for Hardware Synthesis of Reconfigurable Logic Controller

Abstract The paper presents developed synthesis methodology of a hardware implemented reconfigurable logic controller from multiple languages incorporating ladder diagrams, instruction list and sequential functional chart according to IEC61131-3. It is focused on the originally developed a high performance computation model based on properly defined variable access. The method address synthesis process of logic and arithmetic operations. Presented approach is able to synthesize not only basic constructs of languages but also complex modules like timers and counters. The paper acquaint with the compilation of considered languages and complex modules into intermediate form suitable for logic synthesis process according to developed analysis, translation and mapping methods. The data flow graph has been chosen for intermediate representation of a program. An original enhancement of the DFG with attributed edges and specific nodes has been described. It allows for efficient representation and processing of logic and arithmetic formulas. The set of compilation algorithms that preserve effects of serial execution order and offer obtaining massively parallel processing unit are presented.