Andy Wei

Measurement of transient effects in SOI DRAM/SRAM access transistors

Bitline-induced transient effects in access transistors pose a problem in SOI DRAM and SRAM cells. The floating-body potential is affected by the bitline so changes in the bitline potential may upset the charge stored in the memory cell. Transient effects in SOI access transistors are measured versus the time the bitline is at high voltage, and V/sub DD/ for fully- and partially-depleted SOI devices. Bulk devices show no bitline-induced transient effects. Measurements show that the magnitude of the charge upset can be large enough to disturb the charge stored in DRAM and SRAM cells. Measurements also show that for any substantial upsets to occur, the time the bitline has to be at high voltage is on the order of milliseconds. Although the effect of bitline transitions is cumulative, the amount of charge upset when the bitline switches rapidly (i.e., millisecond periods) is shown to be negligible. Thus, proper design of SRAM upset-charge protection and DRAM refresh time should circumvent this problem.

Physically based comparison of hot-carrier-induced and ionizing-radiation-induced degradation in BJTs

A physically based comparison between hot-carrier and ionizing radiation stress in BJTs is presented. Although both types of stress lead to qualitatively similar changes in the current gain of the device, the physical mechanisms responsible for the degradation are quite different. In the case of hot-carrier stress the damage is localized near the emitter-base junction, which causes the excess base current to have an ideality factor of two. For ionizing radiation stress, the damage occurs along all oxide-silicon interfaces, which causes the excess base current to have an ideality factor between one and two for low total doses of ionizing radiation, but an ideality factor of two for large total doses. The different physical mechanisms that apply for each type of stress imply that improvement in resistance to one type of stress does not necessarily imply improvement in resistance to the other type of stress. Based on the physical model, implications for correlating and comparing hot-carrier-induced and ionizing-radiation-induced damage are discussed. >

Effect of floating-body charge on SOI MOSFET design

This work presents a new method for assessing the effect of floating-body charge on a fully- and partially-depleted Silicon-on-Insulator (SOI) MOSFET device design space. Floating-body effects under transient conditions are incorporated into the device design parameters threshold voltage V/sub T/ and off-current I/sub 0FF/ using calibrated two-dimensional (2-D) device simulation. Simulation methodology which reveals the worst-case bounds of the device design parameters, from idle to switching-steady-state, is presented and applied to a CMOS inverter example. Using this methodology, the worst-case shifts in V/sub T/ and I/sub 0FF/ due to hysteretic floating-body charge are quantified for devices in L/sub eff/=0.2- and 0.1-/spl mu/m design spaces. Methods to reduce floating-body effects are discussed including a demonstration of how reducing the effective bulk carrier lifetime widens the 0.1-/spl mu/m design space.

Minimizing floating-body-induced threshold voltage variation in partially depleted SOI CMOS

Pulse propagation problems associated with dynamic floating-body effects, e.g., pulse stretching, is measured in partially depleted SOI CMOS inverter chains. Pulse stretching is found to be dependent on pulse frequency and V/sub DD/. Such behavior is attributed to floating-body-induced transient threshold voltage variation in partially depleted SOI CMOS devices due to floating-body charge imbalance between logic states during CMOS switching. Such an imbalance can be minimized through proper device design because of the different dependencies of the gate and drain depletion charges on channel length, silicon film thickness, gate oxide thickness, channel doping, and supply voltage. This is confirmed by measuring the maximum transient threshold voltage variation in discrete partially depleted SOI NMOS devices in configurations which are predictive of CMOS switching behavior.

Transient behavior of the kink effect in partially-depleted SOI MOSFET's

The behavior of transients in the drain current of partially-depleted (PD) SOI MOSFETs down to L/sub eff/=0.2 /spl mu/m is examined as a function of drain bias, gate pulses of varying magnitude (V/sub GS/), pulse duration, and pulse frequency. At fixed V/sub DS/, the gate is pulsed to values ranging from 0.1 V above V/sub T/ to V/sub GS/=V/sub DS/. A slow transient is seen when the drain is biased at a V/sub DS/ where the current kink is observable. This slow transient can be on the order of microseconds depending on the relative magnitude of the impact ionization rate. For short times after the pulse edge or for very short pulses at low frequencies, it is shown that the subthreshold drain current value can be very different from the corresponding DC, and that the kink characteristic of PD MOSFETs disappears. However, the kink values can be approached when the pulse frequency and/or duration applied to the gate is increased, due to the latent charge maintained in the floating body at higher frequencies. No transient current effects were observed in fully-depleted SOI MOSFETs.<<ETX>>

Excess collector current due to an oxide-trapped-charge-induced emitter in irradiated NPN BJT's

Excess collector current in irradiated NPN BJTs is linked to an oxide-trapped-charge-induced inversion layer acting as an additional emitter. Excess collector current is modeled by interpreting the inversion layer as an extension of the emitter. >

Design methodology for minimizing hysteretic V/sub T/-variation in partially-depleted SOI CMOS

This work demonstrates that switching-history-dependent threshold voltage variation can be minimized in partially-depleted SOI NMOS and PMOS devices by a device design which combines body-charge balance between logic states with minimum gate-body capacitive coupling and non-ideal body-source/drain diode behavior. This analysis also demonstrates that once the devices are charge-balanced supply voltage scaling naturally minimizes /spl Delta/V/sub T/.

Bounding the severity of hysteretic transient effects in partially-depleted SOI CMOS

Hysteretic time-transient floating-body effects are of great concern in designing partially-depleted (PD) SOI circuits. It has been demonstrated that these hysteretic floating-body effects can give rise to irregular signal propagation such as frequency dependent propagation and pulse stretching. However, these floating-body effects are known to offer enhancement of current drive over an equivalent SOI body-contacted device. Thus, it may be desirable to keep the body floating so long as the hysteretic effects can be minimized by proper device design. In order to evaluate a device design for hysteresis effect, a methodology is required which can bound the severity of hysteretic effects. In this work, a simulation method using MEDICI to evaluate PD-SOI MOSFET hysteresis effects is introduced and applied to several device designs. Two designs which eliminate hysteretic floating-body effects in PD-SOI CMOS inverters are demonstrated.

Effect of body-charge on fully- and partially-depleted SOI MOSFET design

This work presents a new method for assessing the effect of floating-body charge on a fully- and partially depleted SOI device design space. Floating-body effects are incorporated into the device design criteria, V/sub T/ and I/sub OFF/ via transient-based evaluation of device performance using calibrated 2-D device simulation. Using this methodology, the worst-case shifts in V/sub T/ and I/sub OFF/ due to hysteretic floating-body charge are quantified for L/sub eff/-0.2 /spl mu/m and 0.1 /spl mu/m design spaces. The effect of reducing effective bulk lifetime in widening the 0.1 /spl mu/m design space is demonstrated.

Accounting for experimentally observed transients in simulation of partially-depleted SOI MOSFET's

This paper has shown that a unique set of carrier lifetime and impact ionization rate can be used to account for both the transient behavior and DC I-V characteristics of a partially-depleted SOI MOSFET. Operation of these devices at low to moderate drain voltages ( 1.0 to 2.0 V) was shown to be strongly related to both impact ionization rate and carrier lifetime.