Melanie J. Sherony

Effect of floating-body charge on SOI MOSFET design

This work presents a new method for assessing the effect of floating-body charge on a fully- and partially-depleted Silicon-on-Insulator (SOI) MOSFET device design space. Floating-body effects under transient conditions are incorporated into the device design parameters threshold voltage V/sub T/ and off-current I/sub 0FF/ using calibrated two-dimensional (2-D) device simulation. Simulation methodology which reveals the worst-case bounds of the device design parameters, from idle to switching-steady-state, is presented and applied to a CMOS inverter example. Using this methodology, the worst-case shifts in V/sub T/ and I/sub 0FF/ due to hysteretic floating-body charge are quantified for devices in L/sub eff/=0.2- and 0.1-/spl mu/m design spaces. Methods to reduce floating-body effects are discussed including a demonstration of how reducing the effective bulk carrier lifetime widens the 0.1-/spl mu/m design space.

Reduction of threshold voltage sensitivity in SOI MOSFET's

The threshold voltage sensitivity, of fully depleted SOI MOSFETs to variations in SOI silicon film thickness was examined through both simulation and device experiments. The concept of designing the channel V/sub th/ implant to achieve a constant dose within the film, rather than a constant doping concentration, was studied for a given range of film thicknesses. Minimizing the variation in retained dose reduced the threshold voltage sensitivity to film thickness for the range of t/sub si/ examined. One-dimensional process simulations were performed to determine the optimal channel implant condition that would reduce the variation in retained dose using realistic process parameters for both NMOS and PMOS device processes. SOI NMOS transistors were fabricated. The experimental results confirmed the simulation findings and achieved a reduced threshold voltage sensitivity.<<ETX>>

SOI MOSFET effective channel mobility

The standard bulk MOSFET definition for effective electric field is modified for SOI devices to account for nonzero electric field at the back oxide interface. The effective channel mobility in fully-depleted n-channel SOI MOSFETs is shown to be independent of applied backgate bias when the modified E/sub eff/ definition is used. The effective channel mobility as a function of E/sub eff/ is also shown to be independent of film thickness for fully-depleted devices. >

Optimization of series resistance in sub-0.2 /spl mu/m SOI MOSFET's

The optimization of device series resistance in ultra-thin film SOI devices is studied through 2-D simulations and process experiments. The series resistance is dependent on the contact resistivity of the silicide to silicon and the silicide geometry. To achieve low series resistance, very thin silicides that do not fully consume the SOI film are needed. A novel cobalt salicidation technology using titanium/cobalt laminates is used to demonstrate sub-0.2 /spl mu/m, thin-film SOI devices with excellent performance and very low device series resistance.<<ETX>>

Transient behavior of the kink effect in partially-depleted SOI MOSFET's

The behavior of transients in the drain current of partially-depleted (PD) SOI MOSFETs down to L/sub eff/=0.2 /spl mu/m is examined as a function of drain bias, gate pulses of varying magnitude (V/sub GS/), pulse duration, and pulse frequency. At fixed V/sub DS/, the gate is pulsed to values ranging from 0.1 V above V/sub T/ to V/sub GS/=V/sub DS/. A slow transient is seen when the drain is biased at a V/sub DS/ where the current kink is observable. This slow transient can be on the order of microseconds depending on the relative magnitude of the impact ionization rate. For short times after the pulse edge or for very short pulses at low frequencies, it is shown that the subthreshold drain current value can be very different from the corresponding DC, and that the kink characteristic of PD MOSFETs disappears. However, the kink values can be approached when the pulse frequency and/or duration applied to the gate is increased, due to the latent charge maintained in the floating body at higher frequencies. No transient current effects were observed in fully-depleted SOI MOSFETs.<<ETX>>

A 4-91-GHz traveling-wave amplifier in a standard 0.12-/spl mu/m SOI CMOS microprocessor technology

This paper presents five-stage and seven-stage traveling-wave amplifiers (TWA) in a 0.12-/spl mu/m SOI CMOS technology. The five-stage TWA has a 4-91-GHz bandpass frequency with a gain of 5 dB. The seven-stage TWA has a 5-86-GHz bandpass frequency with a gain of 9 dB. The seven-stage TWA has a measured 18-GHz noise figure, output 1-dB compression point, and output third-order intercept point of 5.5 dB, 10 dBm, and 15.5 dBm, respectively. The power consumption is 90 and 130 mW for the five-stage and seven-stage TWA, respectively, at a voltage power supply of 2.6 V. The chips occupy an area of less than 0.82 and 1 mm for the five-stage and seven-stage TWA, respectively.

Optimization of series resistance in sub-0.2 /spl mu/m SOI MOSFETs

The optimization of device series resistance in ultra-thin film SOI devices is studied through 2-D simulations and process experiments. To achieve low series resistance, very thin silicides that do not fully consume the SOI film are needed. A novel cobalt salicidation technology using titanium/cobalt laminates is used to demonstrate sub-0.2 /spl mu/m, thin-film SOI devices with excellent performance and very low device series resistance.<<ETX>>

Impact of the gate-to-body tunneling current on SOI history effect

The gate dielectric thickness has been aggressively scaled in recent technology generations. The thin gate dielectric is essential to maintain and improve the performance at reduced supply voltages and to control the short-channel effect. For very thin dielectrics, the gate tunneling current becomes noticeable. A component of this tunneling current is comprised of the body majority carriers tunneling from the body to the gate or vice versa. As a result, in SOI MOSFETs, the floating body potential and the history effect are affected by this current in addition to the diode leakage and impact ionization currents. In this paper, we study the impact of gate-to-body tunneling on SOI history effect for the first time.

Minimization of threshold voltage variation in SOI MOSFETs

SOI NMOS devices incorporating the constant dose design concept were fabricated. The devices had a gate oxide of 8 nm, a buried oxide of 380 nm, and a silicon film thickness (t/sub Si/) that ranged between 42 nm to 53 nm. All measurements were taken on long channel (L/sub eff/>2 /spl mu/m) devices. The devices implanted with the lowest energy of 20 keV are less sensitive to t/sub Si/ variations than those with the higher implant energy conditions. For comparison, the threshold voltage (V/sub T/) calculated from the analytical model of Lim et al. (1983) is also shown for the constant substrate dopings of 3/spl times/10/sup 17/ cm/sup -3/ and 4/spl times/10/sup 17/ cm/sup -3/. The V/sub T/ sensitivity to t/sub Si/ variations was reduced considerably by using the constant dose design concept.

Comparison of plasma-induced charging damage in bulk and SOI MOSFETs

Plasma-induced charging damage was examined on both bulk and SOI n-MOSFETs using time-zero dielectric breakdown measurements. It was found that the TZDB distributions for the SOI devices were less dependent on antenna ratio and less susceptible to antenna charging damage than bulk silicon devices. The dramatically different behavior for SOI implies that the antenna design rule requirements for bulk and SOI MOSFETs will not be the same. Finally, it is noted that antenna damage effects in SOI devices may depend on the size of the silicon island relative to the length scale of the plasma non-uniformity.