Aneesh Nainani

Increase in current density for metal contacts to n-germanium by inserting TiO2 interfacial layer to reduce Schottky barrier height

Metal contacts to n-type Ge have poor performance due to the Fermi level pinning near the Ge valence band at metal/Ge interfaces. The electron barrier height can be reduced by inserting ultrathin dielectrics at the metal-semiconductor interface. However, this technique introduces tunneling resistance from the large conduction band offset (CBO) between the insulator and Ge. In this work, the CBO between TiO2 and Ge is estimated to range from −0.06 to −0.26 eV so tunneling resistance can be reduced. By inserting 7.1 nm TiO2 between Al and n-Ge, current densities increased by about 900× at 0.1 V and 1200× at −0.1 V compared to contacts without TiO2.

Fermi-level unpinning and low resistivity in contacts to n-type Ge with a thin ZnO interfacial layer

We report low resistance Ohmic contacts on n-Ge using a thin ZnO interfacial layer (IL) capped with Ti. A 350°C post metallization anneal is used to create oxygen vacancies that dope ZnO heavily n-type (n+). Rectifying Ti/n-Ge contacts become Ohmic with 1000× higher reverse current density after insertion of n+-ZnO IL. Specific resistivity of ∼1.4×10−7 Ω cm2 is demonstrated on epitaxial n+-Ge (2.5×1019 cm−3) layers. Low resistance with ZnO IL can be attributed to (a) low barrier height from Fermi-level unpinning, (b) good conduction band alignment between ZnO and Ge, and (c) thin tunneling barrier due to the n+ doping.

GeSn technology: Extending the Ge electronics roadmap

First principles study showed indicated band gap of Ge can be tuned by alloying with Sn and metastable GeSn alloys can be synthesized at or above room temperature. Subsequently, high quality GeSn layers were grown using low temperature MBE. PL indicated good crystal quality of GeSn material with a reduced direct bandgap. Challenges involved in CMOS processing on GeSn were addressed through effective surface cleaning and a low thermal budget process flow. To the best of our knowledge this work is the first demonstration of a high-κ pMOSFET using 3% GeSn as channel material showing 20% improvement in hole mobility compared to Ge. Alloying Ge with Sn has thus been shown as a performance booster for Ge based devices. Further improvements in material quality and incorporation of higher substitutional Sn, coupled with strain and bandgap engineering, significant performance gains can be achieved from this alloy system.

High-Mobility Ge N-MOSFETs and Mobility Degradation Mechanisms

Ge N-MOSFETs have exhibited poor drive currents and low mobility, as reported by several different research groups in the past. The major mechanisms behind poor Ge NMOS performance have not been completely understood yet. In this paper, mechanisms responsible for poor Ge NMOS performance in the past are investigated with detailed gate dielectric stack characterizations and Hall mobility analysis. High source/drain (S/D) parasitic resistance, inversion charge loss due to trapping in the high-K gate dielectric, and high interface trap density are identified as the mechanisms responsible for Ge NMOS performance degradation. After eliminating the degradation mechanisms, the highest electron mobility in Ge NMOS to date, which is, to the best of our knowledge, ~1.5 times the universal Si mobility, is experimentally demonstrated for the Ge N-MOSFETs fabricated with ozone-oxidation surface passivation and low temperature S/D activation processes.

Experimental demonstration of high mobility Ge NMOS

The highest electron mobility in Ge NMOS to-date, ∼1.5 times the universal Si mobility, is demonstrated experimentally. Gate stack engineered with ozone-oxidation is integrated with low temperature S/D activation to fabricate Ge NMOS. Mechanisms responsible for poor Ge NMOS performance in the past are investigated with detailed gate dielectric stack characterizations and Hall mobility analyses for the first time. High S/D parasitic resistance, inversion charge loss due to trapping, and high interface trap density are identified as the mechanisms responsible for Ge NMOS performance degradation.

Contact resistivity reduction through interfacial layer doping in metal-interfacial layer-semiconductor contacts

Metal-induced-gap-states model for Fermi-level pinning in metal-semiconductor contacts has been extended to metal-interfacial layer (IL)-semiconductor (MIS) contacts using a physics-based approach. Contact resistivity simulations evaluating various ILs on n-Ge indicate the possibility of forming low resistance contacts using TiO2, ZnO, and Sn-doped In2O3 (ITO) layers. Doping of the IL is proposed as an additional knob for lowering MIS contact resistance. This is demonstrated through simulations and experimentally verified with circular-transfer length method and diode measurements on Ti/n+-ZnO/n-Ge and Ti/ITO/n-Ge MIS contacts.

Device quality Sb-based compound semiconductor surface: A comparative study of chemical cleaning

We have studied the surface cleaning of Sb-based compound semiconductors using HF, NH4OH, and HCl cleans and the metal–oxide–semiconductor (MOS) capacitors fabricated subsequently. GaSb, InGaSb, and AlGaSb surfaces are investigated using low-energy radiation from the synchrotron. Capacitance–voltage (C–V) and photoluminescence measurements are carried out on capacitors made with Al2O3 from atomic layer deposition and corroborated with the results from synchrotron spectroscopy. Excellent C–V characteristics with a mid-band-gap interface state density of 3 × 1011/cm2eV are obtained on samples with the HCl clean. This is consistent with the finding that only the HCl acid clean is able to remove the native oxides present on GaSb and InGaSb surfaces, and produce clean and stable surfaces suitable for MOSFET development. Complete removal of AlOx on the AlGaSb surface was not possible using chemical cleaning. Termination of AlGaSb with two monolayers of GaSb is proposed as a solution.

InxGa1-xSb channel p-metal-oxide-semiconductor field effect transistors: Effect of strain and heterostructure design

InxGa1-xSb is an attractive candidate for high performance III-V p-metal-oxide-semiconductor field effect transistors (pMOSFETs) due to its high bulk hole mobility that can be further enhanced with the use of strain. We fabricate and study InxGa1−xSb-channel pMOSFETs with atomic layer deposition Al2O3 dielectric and self-aligned source/drain formed by ion implantation. The effects of strain and heterostructure design for enhancing transistor performance are studied systematically. Different amounts of biaxial compression are introduced during MBE growth, and the effect of uniaxial strain is studied using wafer-bending experiments. Both surface and buried channel MOSFET designs are investigated. Buried (surface) channel InxGa1−xSb pMOSFETs with peak hole mobility of 910 (620) cm2/Vs and subthreshold swing of 120 mV/decade are demonstrated. Pulsed I-V measurements and low-temperature I-V measurements are used to investigate the physics in transistor characteristics.

Fluorine passivation of vacancy defects in bulk germanium for Ge metal-oxide-semiconductor field-effect transistor application

Vacancy defects in germanium (Ge) adversely impact the electrical performance of Ge based metal-oxide-semiconductor field-effect transistor (MOSFET) in several ways. They behave as an acceptor site, thereby deactivating n-type dopants in the source/drain region. They can also increase substrate leakage currents and impact carrier lifetime in the channel region. In this paper, we characterize and verify the electrical behavior of vacancy defects in Ge using spreading resistance profiling (SRP). Effect of thermal annealing on the vacancy concentration is studied. Finally, passivation of these defects using fluorine (F) ion-implant is shown to demonstrate the feasibility of performance enhancement in Ge-MOSFETs.

Development of high-k dielectric for antimonides and a sub 350°C III–V pMOSFET outperforming Germanium

In<inf>x</inf>Ga<inf>1−x</inf>Sb pMOSFETs with SS of 120mV/decade, I<inf>ON</inf>/I<inf>OFF</inf>>10⁴ and Gm,max of 140/90 mS/mm (L<inf>G</inf>=5µm), fabricated using a self-aligned gate-first process are demonstrated for the first time. Table 2, summarizes the key transistor results. ALD Al<inf>2</inf>O<inf>3</inf> with Dit of 3×10¹¹/cm²eV and strain engineering has enabled a high-mobility In<inf>x</inf>Ga<inf>1−x</inf>Sb pMOSFET an important step toward the implementation of III–V CMOS in future technology nodes.