Udayan Ganguly

Fermi-level unpinning and low resistivity in contacts to n-type Ge with a thin ZnO interfacial layer

We report low resistance Ohmic contacts on n-Ge using a thin ZnO interfacial layer (IL) capped with Ti. A 350°C post metallization anneal is used to create oxygen vacancies that dope ZnO heavily n-type (n+). Rectifying Ti/n-Ge contacts become Ohmic with 1000× higher reverse current density after insertion of n+-ZnO IL. Specific resistivity of ∼1.4×10−7 Ω cm2 is demonstrated on epitaxial n+-Ge (2.5×1019 cm−3) layers. Low resistance with ZnO IL can be attributed to (a) low barrier height from Fermi-level unpinning, (b) good conduction band alignment between ZnO and Ge, and (c) thin tunneling barrier due to the n+ doping.

Design Optimization of Metal Nanocrystal Memory—Part I: Nanocrystal Array Engineering

The three-dimensional (3D) electrostatics together with the modified Wentzel-Kramers-Brillouin tunneling model has been implemented to simulate the programming and retention characteristics of the metal nanocrystal (NC) memories. Good agreements with experimental data are first demonstrated to calibrate the transport parameters. In contrast to previous works, the 3D electrostatic effects investigated in this paper are proven very significant in the memory operations. Therefore, new design criteria of metal NC memories are investigated. Part I presents the physical model and the NC array design optimization. A sparse and large-size NC array, which is suitable for the one-dimensional narrow-channel memories, provides higher program/erase tunneling current density due to the field-enhancement effect and lower charging energy due to the large NC capacitance. On the other hand, to achieve a sufficient memory window, fast programming speed, and long retention time in the typical two-dimensional channel memories, a dense and large-size NC array is favorable while taking the tradeoff with the NC number density into account. Based on the same theoretical model, the authors continue in Part II to consider the design optimization when high-K dielectrics can be employed

Punchthrough-Diode-Based Bipolar RRAM Selector by Si Epitaxy

We propose an epitaxial punchthrough diode for bipolar resistance RAM (RRAM) selector application. Epitaxial Si:C process is used to deposit n+/p/n+ layers which are fabricated into 300-nm-diameter vertical punchthrough diodes. High on-current density of >; 1 MA/cm2 and high on/off current ratio of >; 250 and >; 4700 (at opposite polarities) are observed. A switching speed of <; 10 ns is measured. On-voltage designability is demonstrated by tuning the p-region doping and length. The comparison of experimental IV with Sentaurus TCAD-simulated IV characteristics confirms the punchthrough mechanism. Comparison with other bipolar RRAM selector technologies highlights the overall advantages of punchthrough-based selector.

Carbon nanotube-based nonvolatile memory with charge storage in metal nanocrystals

Ultrathin and narrow semiconductor body on insulator allows aggressive scaling of nonvolatile memories for low power, low read/write voltage, high retention, and high density in comparison with bulk devices. We have fabricated memory cells with single-wall carbon nanotubes as channels and gold nanocrystals as charge storage nodes. The devices have large memory windows with low voltage operations and single-electron-controlled drain currents. Coulomb blockade in nanocrystals combined with single charge sensitivity of the nanotube field-effect transistor can potentially enable multilevel operations. Measured retention time is longer than 6200 s at 10 K, but is only about 800 s at room temperature due to the high leakage in evaporated tunnel oxide used in this study. Better dielectric on nanotubes is expected to greatly improve the room-temperature performance for the nanotube memory device.

Asymmetric electric field enhancement in nanocrystal memories

The electrostatic model for nanocrystal memories is used to illustrate the fundamental difference of the metal nanocrystal memory in low-voltage program/erase (P/E) operations in comparison with semiconductor nanocrystal and trap-based memories. Due to repulsion of potential contours inside conductors, the metal nanocrystals will significantly enhance the electric field between the nanocrystal and the sensing channel set up by the control gate bias and, hence, can achieve much higher efficiency in low-voltage P/E. On the other hand, the electric field originated from the stored charge will only be slightly different for metal and semiconductor nanocrystal cases. We presented the electrostatic models by both approximate analytical formulation and three-dimensional numerical simulation in a nanocrystal array. Operations of P/E and read disturbance were analyzed for the cases of homogeneous charge distribution, silicon, and metal nanocrystals. In the P/E condition of +5/-5 V, the metal nanocrystal memory offers around 1.6 times higher peak fields than Si counterparts and almost three times higher than that from the one-dimensional model for homogeneous charge distribution. The field enhancement factor suggests the design criteria of oxide thickness, nanocrystal size, and spacing. The advantage of asymmetric field enhancement of metal nanocrystals will be even more prominent when high-K gate dielectrics are employed.

Design Optimization of Metal Nanocrystal Memory—Part II: Gate-Stack Engineering

Based on the physical model of nanocrystal (NC) memories described in Part I, a systematic investigation of gate-stack engineering is presented, including high-K control and tunneling oxides. The high-K control oxide enables the effective-oxide-thickness scaling without compromising the memory performance, owing to the low charging energy and large channel-control factor from the three-dimensional electrostatics. The high-K tunneling oxide, on the other hand, improves the retention characteristics utilizing the asymmetric tunneling barrier more effectively away from the direct tunneling regime. Finally, with the optimization strategies introduced in both parts I and II, a metal NC memory design with 1.0-V memory window, 13-mus programming, 2.5-mus erasing, and over 10-year retention time has been demonstrated at plusmn4V operation, which highlights the potential of NC memories as the next-generation nonvolatile memory

Nitride Engineering for Improved Erase Performance and Retention of TANOS NAND Flash Memory

TANOS charge trap flash (CTF) with Al₂O₃-Si₃N₄-SiO₂ memory stack and TaN metal gate is a candidate technology to replace conventional floating gate technology for multi-level NAND applications beyond the 32nm node. The main drawbacks of TANOS to date are poor erase performance (in terms of speed and/or saturated level) as well as insufficient retention in the highest programmed state.

Fermi-Level Pinning in Nanocrystal Memories

The nanocrystal (NC) work-function engineering, which plays an important role on the NC memory characteristics such as memory window and retention time, were long regarded as a matter of choice on NC materials. In this letter, we report opposite polarities of charge storage in Au NC memories with different control oxides. The effective NC work function is found to be not only a bulk property of the NC, but also governed by the interface with surrounding dielectric, as a result of the Fermi-level pinning. By replacing Au NCs with C60 molecules, we also show the pinning effect generally exists at quantum-dot-based devices with high density of interface states. This fundamental interface property should be taken into account in the selection of NC and dielectric materials for the NC memory optimization

ZnO: an attractive option for n-type metal-interfacial layer-semiconductor (Si, Ge, SiC) contacts

We propose ZnO as an attractive interfacial layer (IL) option for n-type metal-IL-semiconductor (MIS) contacts because of (i) good conduction band alignment between ZnO and Si/Ge/SiC, (ii) high n-type doping possible in ZnO, and, (iii) low Fermi-level pinning factor for metal/ZnO contacts. Device simulations suggest better scalability for MIS contacts versus silicides/germanides for future FinFET technologies. Contact diode measurements on Ti/n⁺-ZnO/n-Ge and Ti/n⁺-ZnO/n-Si devices show nearly 1000X increase in current densities due to the presence of an n⁺-ZnO IL. In comparison to alternate IL options such as Al₂O₃ and TiO₂, n⁺-ZnO gives significantly higher current densities on n-Ge as demonstrated through device simulations and experimental data. Specific contact resistivity of (0.8-1.5) × 10^-6 Ω cm² is demonstrated through four-probe measurements on circular TLM devices fabricated on n⁺-Ge (1 × 10¹⁹ cm^-3) epi layers using n⁺-ZnO IL.

Nitride engineering and the effect of interfaces on Charge Trap Flash performance and reliability

The performance and reliability of charge trap flash with single and bi-layer Si-rich and N-rich nitride as the storage node is studied. Single layer devices show lower memory window and poor cycling endurance, and the underlying physical mechanisms for these issues are explained. An engineered trap layer consisting of Si-rich and N-rich nitride interfaced by a SiON barrier layer is proposed. The effect of varying the SiON interfacial layer position on memory window and reliability is investigated. Optimum bi-layer device shows higher memory window and negligible degradation due to cycling (at higher memory window) compared to single layer films. The role of SiON interface in improving the performance and reliability of bi-layer stacks is explained.