Angelo Ciccazzo

An Advanced Clonal Selection Algorithm with Ad-Hoc Network-Based Hypermutation Operators for Synthesis of Topology and Sizing of Analog Electrical Circuits

In electronics, there are two major classes of circuits, analog and digital electrical circuits. While digital circuits use discrete voltage levels, analog circuits use a continuous range of voltage. The synthesis of analog circuits is known to be a complex optimization task, due to the continuous behaviour of the output and the lack of automatic design tools; actually, the design process is almost entirely demanded to the engineers. In this research work, we introduce a new clonal selection algorithm, the elitist Immune Programming, ( eIP ) which uses a new class of hypermutation operators and a network-based coding. The eIP algorithm is designed for the synthesis of topology and sizing of analog electrical circuits; in particular, it has been used for the design of passive filters. To assess the effectiveness of the designed algorithm, the obtained results have been compared with the passive filter discovered by Koza and co-authors using the Genetic Programming ( GP ) algorithm. The circuits obtained by eIP algorithm are better than the one found by GP in terms of frequency response and number of components required to build it.

Support vector machines for surrogate modeling of electronic circuits

In electronic circuit design, preliminary analyses of the circuit performances are generally carried out using time-consuming simulations. These analyses should be performed as fast as possible because of the strict temporal constraints on the industrial sector time to market. On the other hand, there is the need of precision and reliability of the analyses. For these reasons, there is more and more interest toward surrogate models able to approximate the behavior of a device with a high precision making use of a limited set of samples. Using suitable surrogate models instead of simulations, it is possible to perform a reliable analysis in less time. In this work, we are going to analyze how the surrogate models given by the support vector machine (SVM) perform when they are used to approximate the behavior of industrial circuits that will be employed in consumer electronics. The SVM is also compared to the surrogate models given by the response surface methodology using a commercial software currently adopted for this kind of applications.

New coupled EM and circuit simulation flow for integrated spiral inductor by introducing symbolic simplified expressions

Micro-electronics component and circuit design requires long computation time; to reduce this time, the use of simplification techniques has been introduced. In order to obtain a first validation of the method, a first test case is presented; the simplification techniques have been applied to the analytical expression of Y parameters of an inductor equivalent circuit. The resulting expressions have been used in the fitting process in order to reproduce the behaviour of a simulated inductor. Five different optimization algorithms, both deterministic (POWELL and DIRECT) and stochastic (CRS, CRS ENHANCED and OPTIA) have been tested for the fitting. The result of the introduction of the simplification techniques has been the reduction of the running time during the fitting. From an optimization point of view, the best results have been obtained by the stochastic algorithms CRS, and OPTIA.

Derivative-Free Robust Optimization for Circuit Design

In this paper, we introduce a framework for derivative-free robust optimization based on the use of an efficient derivative-free optimization routine for mixed-integer nonlinear problems. The proposed framework is employed to find a robust optimal design of a particular integrated circuit (namely a DC–DC converter commonly used in portable electronic devices). The proposed robust optimization approach outperforms the traditional statistical approach as it is shown in the numerical results.

Smart System Case Studies

This chapter presents two case studies showing how the proposed approach applies to smart system design and optimization. The former is the virtual prototyping platform built for a laser pico-projector actuator, where MEMS, analog and digital components are simulated with the aim of optimizing the resulting image quality by means of firmware tuning. The latter, in the context of wearable equipment for inertial body motion reconstruction, deals with the modeling of an inertial sensor node, supporting system accuracy evaluation and sensor fusion enhancement. Finally, the Open-Source Test Case (OSTC) is described, showing a complete modeling and simulation flow on a publicly available design.

Introduction of Symbolic Simplified Expressions in Circuit Optimization

The computation time required for the analysis and optimization of a complete circuit can be too long. The use of symbolic analysis together with model order reduction techniques can reduce it and make the optimization a practicable way in the circuit design. To evaluate the possibilities offered by the technique, firstly a linear test case has been considered. The problem of an inductor simulation has been analyzed by introducing simplified analytical expressions and different optimization algorithms in the fitting/optimization process. Then the optimization technique has been applied to a real circuit, a voltage reference, trying to improve the stability of the reference over the temperature.

A SVM Surrogate Model-Based Method for Parametric Yield Optimization

Yield optimization is a challenging topic in electronic circuit design. Methods for yield optimization based on Monte Carlo (MC) analysis of a circuit whose behavior is reproduced by simulations usually require too many time expensive simulations to be effective for iterative optimization. In this paper, we propose a method which tackles the yield optimization problem by combining a support vector machine (SVM) surrogate model (SM) of the circuit to perform the MC analysis and evaluate the yield, and an efficient optimization method to maximize the yield evaluated using the SVM SM. We report the numerical results obtained for the design of two real consumer circuits provided by STMicroelectronics, and we compare these results with the ones obtained using the industrial benchmark currently adopted at STMicroelectronics for yield optimization. These preliminary results show that the method is promising to be very efficient and capable of reaching design solutions with high values of the yield.

Waveform Modelling in Order to Speed Up Transient SPICE Simulations

The production of semiconductor integrated circuits is very complex and expensive. Therefore, it is essential to verify the designed circuits before they are fabricated. Due to the process variations, nanoscale circuits have to be simulated many times during the design flow. This kind of analysis can be very expensive because of their complexity and the high number of simulations. For this reason the semiconductor industry is deeply interested in using less complex but accurate models to speed up time consuming SPICE simulations. This contribution presents a method that creates a compact model, which replaces a semiconductor integrated circuit or sub circuit to significantly reduce the transient simulation time.

The MAnON Project

The nano-CMOS technology scaling makes the figures of merit of a circuit, such as performance and power, extremely sensitive to uncontrollable statistical process variation (PV). In this context, multi-objective optimization algorithms and statistical analysis are essential to ensure stable manufacturing and secure high foundry yields. The CAD and Design Services group, part of the IPG R&D in STMicroelectronics, has created a consortium in order to develop, test and implement “Methods for Advanced Multi-objective Optimization for eDFY of Complex Nano-scale Circuits”: the MAnON Project. The contribution presents the industrial and scientific project challenges, the research results, and consequent methodology enhancements and their implementation into a software prototype in order to be usable inside a nanoelectronics industrial design environment.

Yield Optimization in Electronic Circuits Design

In this work we propose an approach that combines a Support Vector learning Machine with a Derivative-Free black box optimization algorithm in order to maximize the yield in the production of electronic circuits. This approach is tested on a circuit provided by ST-Microelectronics, to be employed in consumer electronics. The results of the approach are compared with the results of WiCkeD, a commercial software largely used for integrated circuits analysis.