Salvatore Rinaudo

An Evolutionary Algorithm-Based Approach to Robust Analog Circuit Design using Constrained Multi-Objective Optimization

The increasing complexity of circuit design needs to be managed with appropriate optimization algorithms and accurate statistical descriptions of design models in order to reach the design specifics, thus guaranteeing “zero defects”. In theDesign for Yieldopen problems are the design of effective optimization algorithms and statistical analysis for yield design, which require time consuming techniques. New methods have to balance accuracy, robustness and computational effort. Typical analog integrated circuit optimization problems are computationally hard and require the handling ofmultiple, conflicting, and non-commensurate objectives having strong nonlinear interdependence. This paper tackles the problem by evolutionary algorithms to produce tradeoff solutions. In this research work, Integrated Circuit (IC) design has been formulated as a constrained multi-objective optimization problem defined in a mixed integer/ discrete/continuous domain. TheRF Low Noise Amplifier, Leapfrog Filter, and Ultra Wideband LNA real-life circuits were selected as test beds. The proposed algorithm, A-NSGAII, was shown to produce acceptable and robust solutions in the tested applications, where state-ofart algorithms and circuit designers failed. The results show significant improvement in all the chosen IC design problems.

Trapping and Thermal Effects Analysis for AlGaN/GaN HEMTs by Means of TCAD Simulations

The aim of this letter is to gain insights into the thermal effects and trapping phenomena of AlGaN/GaN high electron mobility transistors by means of 2-D numerical simulations. Starting from experimental pulsed measurements, we study not only the gate/drain lag due to trap phenomena, but also the thermal behavior of such transistors. Actually, transient tests are useful both to analyze the self-heating effect and to characterize donor surface traps and acceptor bulk traps.

Distributed Modeling of Layout Parasitics in Large-Area High-Speed Silicon Power Devices

This paper reports a technique for generating a lumped-element distributed model for silicon power devices that takes into account the effect of layout parasitics. The proposed methodology exploits the high-frequency modeling approach of microstrips and striplines to describe both the passive parts of the device and elementary transistor cells. A semi-empirical model for the elementary transistor cells of the power device is also proposed. Parameter extraction is described and validated by direct comparison with device simulations of an actual device. The proposed modeling approach is employed to investigate the internal current distribution of a high-voltage silicon power MOSFET supplied by STMicroelectronics during the turnoff transient. The tradeoff that must be accomplished between accuracy and complexity is discussed. The effect of increased switching frequency on the device current distribution is also reported explaining how it may lead to performance degradation and device failure.

A Top-Down Constraint-Driven Methodology for Smart System Design

Smart Systems collate leading technologies and solutions for the design of new generation embedded and cyber-physical systems. They can be applied to a broad range of application domains, from everyday life to mission and safety critical tasks, and achieve a wide set of functionality using diverging architectures. Smart system design needs to be achieved in a real multi-domain environment, where analog, digital, mixed-signal, and now even MEMS sub-systems tightly interact. With a traditional approach, these different units are designed separately, and finally merged at the electronic system level. However, given the increasing integration and interactions among components of different nature, methodologies enabling effective system-level architectural exploration are becoming more and more significant. Starting from a detailed analysis and classification of state-of-the-art use scenarios, and based on a review of the existing approaches, we present a top-down constraint-driven methodology for the design of new generation smart systems. It enables partitioning and propagation of high-level application-driven requisites towards low-level units in the design flow. The methodology reviews fundamental and cross-sectional system-level design aspects applied to the definition of an example case, to identify sub-system requirements towards the specifications of the electrical features of each internal unit.

Investigating the effects of inverted temperature dependence (ITD) on clock distribution networks

The aggressive scaling of CMOS technology toward nanometer lengths contributed to the surfacing of many effects that were not appreciable at the micrometer regime. Among them, Inverted Temperature Dependence (ITD) is certainly the most unusual. It manifests itself as a speed up of CMOS gates when the temperature increases, resulting in a reversal of the worst-case condition, i.e., CMOS gates show the largest delay at low temperatures. On the other hand, for metal interconnects an high temperature still holds as worst case condition. The two contrasting behaviors may invalidate the results obtained through standard design flow which do not consider temperature as an explicit variable in their optimizations. In this paper we focus on the impact of ITD on clock distribution networks (CDN), whose function is vital to guarantee the synchronization among physically spaced sequential components of digital circuits. Using our simulation framework, we characterized the thermal behavior of a clock tree mapped onto an industrial 65nm CMOS technology and obtained using a standard synthesis tool. Results demonstrate the presence of ITD at low operating voltages and open new potential research scenarios into the EDA field.

New coupled EM and circuit simulation flow for integrated spiral inductor by introducing symbolic simplified expressions

Micro-electronics component and circuit design requires long computation time; to reduce this time, the use of simplification techniques has been introduced. In order to obtain a first validation of the method, a first test case is presented; the simplification techniques have been applied to the analytical expression of Y parameters of an inductor equivalent circuit. The resulting expressions have been used in the fitting process in order to reproduce the behaviour of a simulated inductor. Five different optimization algorithms, both deterministic (POWELL and DIRECT) and stochastic (CRS, CRS ENHANCED and OPTIA) have been tested for the fitting. The result of the introduction of the simplification techniques has been the reduction of the running time during the fitting. From an optimization point of view, the best results have been obtained by the stochastic algorithms CRS, and OPTIA.

Modeling of thermal network in silicon power MOSFETs

In this work we propose a methodology to define an equivalent resistive thermal network that allows to model the lateral heat propagation through the silicon substrate of power devices. The basic idea is to split the substrate in basic elements of length ΔL and to associate to each element, lumped thermal resistances. The proposed model is validated by comparison with electro-thermal numerical simulations in silicon Power MOSFET technology. The proposed thermal network accurately predicts the temperature increase as a function of the distance from the heat source.

Parallel Implementation in a Industrial Framework of Statistical Tolerancing Analysis in Microelectronics

The aim of this work is to report on a parallel implementation of methods for tolerance analysis in the framework of a microelectronics design center. The methods were designed to run parallelly on different platforms which could have different computational performances. In order to distribute the computations over a network of workstations, the algorithm was designed not by using a parallel compiler, but by using a RPC multi-server network. We have used essentially two methods. The first is the Monte Carlo approach, the second is based on an approximation by numerical integration or quadrature technique [1, 2, 3, 4], which requires far less function evaluations than the Monte Carlo method. These two approaches have been implemented in a parallel algorithm to be used on a cluster of multivendor workstations.

Small-signal and noise modeling of submicrometer self aligned bipolar transistor

This paper presents an approach to get a full characterization of microwave bipolar transistors starting from S-parameters measurement only. The analytical form of the Y-matrix representation is derived starting from the /spl pi/-hybrid model (Giacoletto, 1954) and it is used to directly and accurately extract all the parameters of the model. In the second part of the paper the noise sources are added to the equivalent model, and the analytical expression of noise figure is obtained. This expression is used to obtain a full set of noise parameters to characterize the behaviour of the bipolar microwave transistors.

Towards Multi-Domain and Multi-Physical Electronic Design

Electronic systems are increasingly fusing multiple technology solutions exchanging information both at electrical and at non-electrical levels, and in general both analog and digital operation coexists in multiple physical domains. This paper introduces a homogeneous multi-domain design methodology which blurs analog and digital boundaries and enables the design of etherogeneous electrical and non-electrical building blocks. The methodology is based on the identification of four fundamental quantities (quadrivium), namely signal-to-noise ratio, signal-to-interference ratio, impedance and consumed energy, applicable to both electrical and multiphysics components. Based on their constraining and their propagation on an ensemble of transactions in time domain, these four elements can be used across different domains (digital or analog), and permit architects to extract internal features, so that these are intrinsically oriented to successive physical and technology-related implementation and modeling. With example application cases, we show that these four quantities in turn define design constraints of electrical and nonelectrical internal units. After presenting an electronic design example, to show applicability in multiple physical domains, the paper discusses and applies the quadrivium also in the context of a MEMS sensor and microfluidic components.