Angus Wu

Programmable impulse neural circuits

A description is given of CMOS electronic circuits which emulate natural neurons at a more detailed level than that typically used by artificial neural network models. A pulse-firing circuit which realizes general short-term neuron dynamics is discussed. Both fixed and programmable synapse circuits for realizing long-term dynamics are also described. Together, these establish the basic structures required for the implementation of programmable impulse neural networks.

Implementation of a decoupled optimization technique for design of switching regulators using genetic algorithms

This paper presents an implementation of a decoupled optimization technique for design of switching regulators using genetic algorithms (GAs). The optimization process entails the selection of component values in a switching regulator, in order to meet the static and dynamic requirements. Although the proposed method inherits characteristics of evolutionary computations that involve randomness, recombination, and survival of the fittest, it does not perform a whole-circuit optimization. Thus, intensive computations, that are usually found in stochastic optimization techniques can be avoided. Similar to many design approaches for power electronics circuits, a regulator is decoupled into two components, namely the power conversion stage (PCS) and the feedback network (FN). The PCS is optimized with the required static characteristics, whilst the FN is optimized with the required static and dynamic behaviors of the whole system. Systematic optimization procedures are described and the technique is illustrated with the design of a buck regulator with overcurrent protection. The predicted results are compared with the published results available in the literature and are verified with experimental measurements.

On the use of current control scheme for switched-capacitor DC/DC converters

This paper presents an investigation into the use of a current control scheme (CCS) and a comparison with a classical switching scheme for switched-capacitor (SC) step-down DC/DC converters. With the CCS, capacitors are charged with near-constant current, controlled by the gate-source voltage of MOSFETs. By paralleling two SC cells, the converter input current becomes continuous, resulting in much reduced conducted electromagnetic interference with other circuits fed by the same power supply. All MOSFETs are operated for half of the switching period, in order to improve the regulation capability. Static and dynamic behaviors of the converter with the CCS are predicted and confirmed in an experimental 36 W 12 V/9 V prototype.

Fast diagnosis of integrated circuit faults using feedforward neural networks

Presents experimental results which show that feedforward neural networks are suitable for analog IC fault diagnosis. The results suggest that feedforward networks provide a cost-efficient method for IC fault diagnosis in large-scale production. The authors compare the diagnostic accuracy and the computational requirements of a simple feedforward network against that of Gaussian maximum likelihood and K-nearest neighbors classifiers. The feedforward network was found to provide an order-of-magnitude improvement in diagnostic speed while consistently performing as well as or better than any of the other classifiers in terms of accuracy.<<ETX>>

Decoupled optimization technique for design of switching regulators using genetic algorithms

This paper presents a decoupled optimization technique for design of switching regulators using genetic algorithms (GA). The optimization entails selection of the component values in the regulator to meet some static and dynamic requirements. During the optimization, a regulator is decoupled into two parts, including the power conversion stage (PCS) and the feedback network (FN). The PCS is optimized with the required static characteristics, while the FN is optimized with the required static and dynamic characteristics of the whole system during disturbances. The proposed technique is illustrated with the design of a buck regulator. Predicted results are compared to the available literature and are verified with experimental measurements.

Pseudo-coevolutionary genetic algorithms for power electronic circuits optimization

This paper presents pseudo-coevolutionary genetic algorithms (GAs) for power electronic circuit (PEC) optimization. Circuit parameters are optimized through two parallel co-adapted GA-based optimization processes for power conversion stage and feedback network, respectively. Each process has tunable and untunable parametric vectors. The best candidate of the tunable vector in one process is migrated into the other process as untunable vector through a migration controller, in which the migration strategy is adaptively controlled by a first-order projection of the maximum and minimum bounds of the fitness value in each generation. Implementation of this method is suitable for systems with parallel computation capacity, resulting in considerable improvement of the training speed. Optimization of a buck regulator for meeting requirements under large-signal changes and at steady state is illustrated. Simulation predictions are verified with experimental results.This correspondence presents pseudocoevolutionary genetic algorithms (GAs) for power electronic circuit (PEC) optimization. Circuit parameters are optimized through two parallel coadapted GA-based optimization processes for the power conversion stage (PCS) and feedback network (FN), respectively. Each process has tunable and untunable parametric vectors. The best candidate of the tunable vector in one process is migrated into the other process as an untunable vector through a migration controller, in which the migration strategy is adaptively controlled by a first-order projection of the maximum and minimum bounds of the fitness value in each generation. Implementation of this method is suitable for systems with parallel computation capacity, resulting in considerable improvement of the training speed. Optimization of a buck regulator for meeting requirements under large-signal changes and at steady state is illustrated. Simulation predictions are verified with experimental results

Measurement selection for parametric IC fault diagnosis

This article presents experimental results which show feedforward neural networks are well-suited for analog IC fault diagnosis. Boundary band data (BBD) measurement selection is used to reduce the computational overhead of the FFN training phase. We compare the diagnostic accuracy between traditional statistical classifiers and feedforward neural networks trained with various measurement selection criteria. The feedforward networks consistently perform as well as or better than the other classifiers in term of accuracy. Training using BBD consistently reduces the FFN training efforts without degrading the performance. Experimental results suggest that feedforward networks provide a cost efficient method for IC fault diagnosis in a large scale production testing environment.

Neural network diagnosis of IC faults

The authors present experimental results which show that feedforward neural networks are well suited for analog IC fault diagnosis. Their results suggest that feedforward networks provide a cost efficient method for IC fault diagnosis in a large scale production environment. They specifically compare the diagnostic accuracy and the computational requirements of a simple feedforward network against that of Gaussian maximum likelihood and K-nearest neighbors classifiers. The feedforward network is found to provide an order-of-magnitude improvement in diagnostic speed while consistently performing as well as or better than any of the other classifiers in terms of accuracy. This makes the feedforward network classifier an excellent candidate for production line diagnosis of IC faults, where circuit verification time greatly influences total cost per part.<<ETX>>

On the use of pseudo-coevolutionary genetic algorithms with adaptive migration for design of power electronics regulators

This paper presents the use of pseudo-coevolutionary genetic algorithms for design of power electronics regulators. By using the decoupled optimization technique, the component values of the power conversion stage and feedback network are optimized with two coadapted evolutionary training processes, in which they are classified as two isolated species and are evolved in parallel. Components from one species will asynchronously migrate into collaborations for training another species when that component set has significant enhancement in the overall regulator performance. An adaptive migration rate that improves the overall training process is proposed. This modular approach decentralizes computations and is suitable for network-based optimization. The proposed technique is illustrated with the design of a buck regulator.

Fast, area-efficient CMOS parity generation

High-performance CMOS parity generator cells are described. Their enhanced speed is derived principally from a combination of exclusive-or and equivalence gate circuits. The circuits realize these logic functions in a single gate level using a combination of fully restoring and pass-transistor gate topology in a semirestoring configuration. The circuits are suitable for the gate forest realization. These parity generator cells neither consume DC power nor require complementary input signals, and are approximately three to five times faster than the conventional dual-level logic implementation. When these circuits are cascaded, the noise margin degradation problems typically associated with nonrestoring logic families are improved. The simplicity of this approach provides significant area savings compared to conventional implementations of various types.<<ETX>>