Jack L. Meador
Washington State University
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Featured researches published by Jack L. Meador.
IEEE Transactions on Neural Networks | 1991
Jack L. Meador; Angus Wu; Clint S. Cole; N. Nintunze; Pichet Chintrakulchai
A description is given of CMOS electronic circuits which emulate natural neurons at a more detailed level than that typically used by artificial neural network models. A pulse-firing circuit which realizes general short-term neuron dynamics is discussed. Both fixed and programmable synapse circuits for realizing long-term dynamics are also described. Together, these establish the basic structures required for the implementation of programmable impulse neural networks.
Neural Networks | 1991
Wayne Joerding; Jack L. Meador
Abstract Theoretical results and practical experience indicate that feedforward networks are very good at approximating a wide class of functional relationships. Training networks to approximate functions takes place by using exemplars to find interconnect weights that maximize some goodness of fit criterion. Given finite data sets it can be important in the training process to take advantage of any a priori information regarding the underlying functional relationship to improve the approximation and the ability of the network to generalize. This paper describes methods for incorporating a priori information of this type into feedforward networks. Two general approaches, one based upon architectural constraints and a second upon connection weight constraints form the basis of the methods presented. These two approaches can be used either alone or in combination to help solve specific training problems. Several examples covering a variety of types of a priori information, including information about curvature, interpolation points, and output layer interrelationships are presented.
international symposium on circuits and systems | 1992
Tai-Shan Lin; Jack L. Meador
Complexity reduction and automatic test point selection are discussed in the context of statistical pattern classification. Different types of feedforward neural networks capable of IC fault diagnosis are examined. To reduce diagnostic complexity, principal component analysis (PCA) and full stepwise feature selection are employed to reduce network input dimension without sacrificing accuracy. For fault analysis purposes, it seems that feature selection by stepwise variable selection appears much more useful than feature extraction by PCA, since the latter requires that all original test measurements be made while the former helps eliminate redundant measurements.<<ETX>>
international symposium on circuits and systems | 1992
David Watola; David Gembala; Jack L. Meador
This paper introduces MOS circuits for the integrated implementation of competitive learning. A singlelayer competitive network architecture composed of asynchronous-pulse-coded processing elements is employed. The processing elements perform analog computations and communicate via asynchronous-pulse-density-modulated signals which encode continuous-time signal information using discrete binary values. The specific focus is upon the design and simulation of an adaptive synapse circuit which combines a capacitive analog storage element with subthreshold adaptation circuitry. The simulations presented verify circuit operation in a two-input, three-output competitive network. Accurate clustering of both fixed and random training data is demonstrated.
international symposium on neural networks | 1991
Jack L. Meador; Angus Wu; C.T. Tseng; Tai-Shan Lin
Presents experimental results which show that feedforward neural networks are suitable for analog IC fault diagnosis. The results suggest that feedforward networks provide a cost-efficient method for IC fault diagnosis in large-scale production. The authors compare the diagnostic accuracy and the computational requirements of a simple feedforward network against that of Gaussian maximum likelihood and K-nearest neighbors classifiers. The feedforward network was found to provide an order-of-magnitude improvement in diagnostic speed while consistently performing as well as or better than any of the other classifiers in terms of accuracy.<<ETX>>
Archive | 1994
Jack L. Meador; Paul Hylander
This chapter introduces a pulse-coded winner-take-all (PWTA) network which employs a unique combination of presynaptic and lateral inhibition that can be efficiently implemented in VLSI. The manner in which the network not only selects the winner but also indicates the weight of the decision made is unique among established winner-take-all networks. A combination of all-ornothing and graded responses is encoded as a variable rate pulse train appearing only at the output of the winning unit. The mechanism used is closely related to the presynaptic inhibition approach introduced in [Yuille 88] with the exception that it is self-resetting and has properties which make it well suited for electronic realizations using asynchronous pulse-coded circuitry.
international symposium on circuits and systems | 1995
Jack L. Meador
This paper describes a new approach for shortest path optimization using a recurrent neural network. Network temporal and spacial properties are independently exploited in a manner which generalizes upon earlier Hopfield net optimization approaches. The new spaciotemporal method encodes constraints as a spacially distributed energy and costs as time delays incurred during network convergence. This approach yields a robust recurrent neural network for solving single-source shortest path problems. The approach is suitable for the determination of unique solutions as well as the case where multiple solutions exist. In addition, the new method exhibits better space and time complexity than a Hopfield network approach to the same problem.
Journal of Electronic Testing | 1994
Angus Wu; Jack L. Meador
This article presents experimental results which show feedforward neural networks are well-suited for analog IC fault diagnosis. Boundary band data (BBD) measurement selection is used to reduce the computational overhead of the FFN training phase. We compare the diagnostic accuracy between traditional statistical classifiers and feedforward neural networks trained with various measurement selection criteria. The feedforward networks consistently perform as well as or better than the other classifiers in term of accuracy. Training using BBD consistently reduces the FFN training efforts without degrading the performance. Experimental results suggest that feedforward networks provide a cost efficient method for IC fault diagnosis in a large scale production testing environment.
international symposium on neural networks | 1992
Jack L. Meador
The dynamic behavior of a unique pulse-coded winner-take-all (PWTA) mechanism is described. Parameters which affect PWTA mechanism dynamics are discussed. It is shown that three distinct kinds of behavior can be observed in the vicinity of winning unit boundaries. The first occurs in the infinite precision case where boundaries exhibit ideal behavior. With finite parameter precision, either hysteresis or multiple unit response can be observed over transition regions in the vicinity of ideal boundaries. The interconnect properties of this network make it an attractive candidate for IC implementation.<<ETX>>
vlsi test symposium | 1991
Angus Wu; Tai-Shan Lin; C.T. Tseng; Jack L. Meador
The authors present experimental results which show that feedforward neural networks are well suited for analog IC fault diagnosis. Their results suggest that feedforward networks provide a cost efficient method for IC fault diagnosis in a large scale production environment. They specifically compare the diagnostic accuracy and the computational requirements of a simple feedforward network against that of Gaussian maximum likelihood and K-nearest neighbors classifiers. The feedforward network is found to provide an order-of-magnitude improvement in diagnostic speed while consistently performing as well as or better than any of the other classifiers in terms of accuracy. This makes the feedforward network classifier an excellent candidate for production line diagnosis of IC faults, where circuit verification time greatly influences total cost per part.<<ETX>>