Anil G. Khairnar

Sol–gel deposited ceria thin films as gate dielectric for CMOS technology

In this work, cerium oxide thin films were prepared using cerium chloride heptahydrate, ethanol and citric acid as an additive by sol–gel spin-coating technique and further characterized to study the various properties. Chemical composition of deposited films has been analysed by FTIR which shows existence of CeO2. The samples have been optically characterized using ellipsometry to find refractive index of 2·18 and physical thickness which is measured to be 5·56 nm. MOS capacitors were fabricated by depositing aluminum (Al) metal using the thermal evaporation technique on the top of CeO2 thin films. Capacitance–voltage measurement was carried out to calculate the dielectric constant, flat-band voltage shift of 18·92, 0·3–0·5 V, respectively and conductance–voltage study was carried out to determine the Dit of 1·40 × 1013 eV − 1 cm − 2 at 1 MHz.

Electrical properties of MOS capacitors formed by PEALD grown Al2O3 on silicon

In the present work, we have grown 2.83 nm thin Al2O3 films directly on pre-cleaned p-Si (100) substrate using precursor Trimethyl Aluminium (TMA) with substrate temperature of 300°C in a Plasma Enhanced Atomic Layer Deposition (PEALD) chamber. The MOS capacitors were fabricated by depositing Pt/Ti metal bilayer through shadow mask on Al2O3 high-k by electron beam evaporation system. The MOS devices were characterized to evaluate the electrical properties using a capacitance voltage (CV) set-up. The dielectric constant calculated through the CV analysis is 8.32 for Al2O3 resulting in the equivalent oxide thickness (EOT) of 1.32 nm. The flat-band shift of 0.3 V is observed in the CV curve. This slight positive shift in flat-band voltage is due to the presence of some negative trap charges in Pt/Ti/ALD-Al2O3/p-Si MOS capacitor. The low leakage current density of 3.08 × 10−10 A/cm2 is observed in the JV curve at 1 V. The Si/Al2O3 barrier height ΦB and the value of JFN are calculated to be 2.78 eV and 3.4 × 10−5 A/cm2 respectively.

High Dielectric Constant ZrO2 Films by Atomic Layer Deposition Technique on Germanium Substrates

Germanium has been reconsidered as a potential substitute channel material for high-performance MOSFETs due to its intrinsic high mobilities for both electrons (3900 cm2 s-1V-1) and holes (1900 cm2 s-1V-1). In the present work we have fabricated Pt/Ti metal bilayered ALD-ZrO 2/n-Ge based MOS capacitors. The ZrO2 thin film was deposited on n-Ge (100) substrates by using ZrEMA and oxygen precursors at 300 °C in a PEALD system. The Pt/Ti bilayer metallization was carried out using e-beam evaporation and PMA using a RTA system at 350 °C in the forming gas. The thickness of the ZrO2 gate stack was measured to be 3.61 nm using an ellipsometer. The electrical study was done by analyzing capacitance voltage and current voltage measurements. The flat-band shift was found to be 0.22 V, Qeff was 3.55×1012 cm-2 and Dit was 8.53×1012 cm-2 eV-1. Current voltage characteristics have been analyzed to know the conduction mechanism in fabricated MOS devices.

Investigation of Current Conduction Mechanism in HfO2 Thin Film on Silicon Substrate

In this work, we have investigated current conduction mechanisms in HfO2 thin film deposited on silicon substrate by RF sputtering technique. The thin films of HfO2 were deposited on p-type silicon substrates. FTIR measurement shows the presence of hafnium in the film. Among the various conduction mechanisms the 13.7 nm thin HfO2 film on Si follows the Fowler–Nordheim (FN) tunneling. The Poole–Frenkel (PF) emission, Schottky emission (SE) and Direct Tunneling (DT) also studied. The barrier height (ϕB) of 0.74 eV is calculated from experimental work through Fowler–Nordheim tunneling mechanism.

Capacitance-Voltage Measurement of SiO2/GeOxNy Gate Stack on Surface Passivated Germanium

Germanium (Ge) based MOS transistors is possible alternative to silicon based MOS transistors due to high mobility of carriers in Ge. Extensive research is going on for fabrication of high mobility MOS devices worldwide. Here, we have studied the c-v characteristics of Ge based surface passivated MOS structure such as dielectric constant of gate stack, effective oxide charges, density of interface charges at semiconductor oxide interface etc. The interface trap density extracted from the C-V/G-V measurement showed the lowest interface trap density of 7.82 × 1011 cm2 eV−1. The minimum leakage current density for SiO2/GexONy gate dielectric stack is 1.35 × 10−7 A cm−2 at gate bias of 1 V.

PEALD grown high-k ZrO2 thin films on SiC group IV compound semiconductor

The study of ZrO2 thin films on SiC group IV compound semiconductor has been studied as a high mobility substrates. The ZrO2 thin films were deposited using the Plasma Enhanced Atomic Layer Deposition System. The thickness of the thin films were measured using ellipsometer and found to be 5.47 nm. The deposited ZrO2 thin films were post deposition annealed in rapid thermal annealing chamber at temperature of 400°С. The atomic force microscopy and X-гау photoelectron spectroscopy has been carried out to study the surface topography, roughness and chemical composition of thin film, respectively.