Anil Indluru

Effect of Mechanical and Electromechanical Stress on a-ZIO TFTs

In this letter, we report the effects of electromechanical and mechanical strain on amorphous ZIO thin-film transistors (TFTs), deformed on cylindrical surfaces of varying radii for varying time spans. The TFTs were fabricated on island structures on polyethylene napthalate and subjected to both tensile and compressive stress, parallel and perpendicular to the conducting channel length. Mobility increased while the subthreshold slope decreased with tensile stress, and reverse changes were observed with compressive stress, both being parallel to the channel length. Almost no changes were observed for perpendicular stress, within experimental errors. The magnitude of change also depended on the time duration of the strain. None of the changes were catastrophic to cause complete failure of the devices.

Effects of Gamma Irradiation and Electrical Stress on a-Si:H Thin-Film Transistors for Flexible Electronics and Displays

The change in electrical characteristics of a-Si:H thin-film transistors (TFTs) was determined in the presence of electrical gate bias stress, gamma radiation, and both simultaneously, simulating the harsh environment of space. Multiple TFTs were tested under each condition, and the current-voltage characteristics were measured. The results show the gate bias stress increasing the threshold voltage (VT) with power law time dependence while the gamma irradiation decreases threshold voltage for all working transistors. When both the irradiation and gate bias stress were applied simultaneously, the VT initially increased with electrical stress and then decreased as the gamma radiation dominated. Changes in effective mobility were also extracted and detailed analysis of the current-voltage characteristics indicated that the gamma radiation creates interface traps and electron-hole pairs whereas the gate stress produces defect states in the amorphous silicon.

Effect of Anneal Time on the Enhanced Performance of a-Si:H TFTs for Future Display Technology

Hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) are widely used as controlling devices for picture pixels in liquid crystal displays. In addition to flat panel display applications, a significant research effort focuses on the extension of this technology to circuitry on flexible substrates to build flexible sensor systems. This study investigates the effect of anneal time on the performance of the a-Si:H TFTs on Polyethylene naphthalate (PEN). Off-current is reduced by two orders of magnitude for 48-hours annealed TFT, and the sub-threshold slope become steeper with longer annealing. For positive gate-bias-stress, ΔVt values are positive and exhibit a power-law time dependence (PLTD). The 48-hour annealed TFTs, however, display a turnaround phenomenon (TP) at longer stress times. For negative gate-bias-stress, TFTs annealed for ≥ 24 hours possess a smaller positive ΔVt. They do not follow a PLTD and the TP is observed at longer stress times. The observed ΔVt is explained in terms of the shift in the electron and hole transfer characteristics.

High-Temperature Stability and Enhanced Performance of a-Si:H TFT on Flexible Substrate Due to Improved Interface Quality

We have investigated the effect of anneal time on the performance and temperature-dependent stability of low-temperature-fabricated (180°C) hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) on flexible substrates. For TFTs annealed for 48 h, the subthreshold slope and off-current were reduced by a factor of ~3 and by two orders of magnitude, respectively, when compared to unannealed TFTs. Furthermore, longer annealed TFTs showed a significant improvement in their stability when compared to unannealed TFTs. The lifetime values for the 48- and 96-h-annealed TFTs improved by a factor of ~3 compared to unannealed TFTs when the threshold voltage shift is extrapolated to 10 V. Stability at high temperatures with better lifetimes for the longer annealed TFTs is due to improvement in the a-Si:H/SiNx interface quality by the reduction of trapped charges inside the insulator. For all the TFTs at a positive gate bias, ΔVt follows a power law dependence with time, indicating state creation. A low β value (0.6 for unannealed TFTs to 0.37 for 96-h-annealed TFTs) indicates a good-quality a-Si:H channel and/or the a-Si:H/insulator interface after longer anneals.

Current-Density Dependence on Ag eFUSEs With TiN Underlayers

Silver-based metallization has been studied for a potential application as an electrically programmable fuse (eFUSE) device by local Joule heating induced at high current densities. Three different line widths (3.8, 6.3, and 10 mum) are investigated by subjecting them to extremely high current-density conditions. Based on short median lifetime and the topography of the failure sites, the dominant failure mechanism in Ag eFUSEs with TiN barrier layer under these current densities is examined. Evaporation times have also been calculated to correlate the Ag properties with the median failure time. The barrier layer has an important role to play in determining the failure time in these types of eFUSEs.