David R. Allee

Selective area oxidation of silicon with a scanning force microscope

The use of a scanning force microscope with a metallized tip to do selective area oxidation of silicon is demonstrated. Sub‐100 nm lines have been achieved. Removal of the oxide lines with buffered hydrofluoric acid reveals trenches in the silicon consistent with silicon consumption in SiO2 formation.

Thickness dependence on the thermal stability of silver thin films

This study investigates the dependence of Ag resistivity on film thickness during temperature ramping as a means to access thermal stability. In situ van der Pauw four-point probe analysis is used to determine the onset temperature; the temperature when the electrical resistivity deviates from linearity during the temperature ramp. At that point, the silver thin films become unstable due to void formation and growth during thermal annealing. The thermal stability of Ag thin films on SiO2 in a vacuum is greatest when thicknesses are greater than 85 nm. Using an Arrhenius relation in terms of onset temperature and film thickness, an activation energy (0.32±0.02 eV) for the onset of agglomeration in Ag thin films on SiO2 ramped at a rate of 0.1 °C/s is determined. This value is consistent with the activation energy for surface diffusion of silver in a vacuum, which is believed to be the dominant mechanism for agglomeration of silver thin film.

Direct nanometer scale patterning of SiO2 with electron beam irradiation through a sacrificial layer

Nanometer scale patterns have been fabricated in SiO2 by electron beam exposure through a sacrificial layer. Although the process of patterning SiO2 with direct electron beam irradiation was discovered over two decades ago, the smallest feature size previously achieved was 0.6 μm because finely focused electron beams form a contamination layer on the substrate blocking the subsequent development of the oxide with HF wet etches. Exposing through a sacrificial layer, the contamination is readily removed with the stripping of the sacrificial layer. Using high energy electrons (300 keV) to minimize forward scattering of the beam, arrays of lines with a period down to 21 nm have been fabricated in the SiO2.

Design, Simulation, Fabrication and Testing of Flexible Bow-Tie Antennas

Design, simulation, fabrication and measurement of two different novel flexible bow-tie antennas, a conventional and a modified bow-tie antenna with reduced metallization, are reported in this paper. The antennas are mounted on a flexible substrate fabricated at the Flexible Display Center (FDC) of Arizona State University (ASU). The substrate is heat stabilized polyethylene naphthalate (PEN) which allows the antennas to be flexible. The antennas are fed by a microstrip-to-coplanar feed network balun. The reduction of the metallization is based on the observation that the majority of the current density is confined towards the edges of the regular bow-tie antenna. Hence, the centers of the triangular parts of the conventional bow-tie antenna are removed without compromising significantly its performance. The return losses and radiation patterns of the antennas are simulated with HFSS and the results are compared with measurements, for bow-tie elements mounted on flat and curved surfaces. The comparisons show that there is an excellent agreement between the simulations and measurements for both cases. Furthermore, the radiation performance of the modified bow-tie antenna is verified, by simulations and measurements, to be very close to the conventional bow-tie.

Low-temperature amorphous-silicon backplane technology development for flexible displays in a manufacturing pilot-line environment

— A low-temperature amorphous-silicon (a-Si:H) thin-film-transistor (TFT) backplane technology for high-information-content flexible displays has been developed. Backplanes were integrated with frontplane technologies to produce high-performance active-matrix reflective electrophoretic ink, reflective cholesteric liquid crystal and emissive OLED flexible-display technology demonstrators (TDs). Backplanes up to 4 in. on the diagonal have been fabricated on a 6-in. wafer-scale pilot line. The critical steps in the evolution of backplane technology, from qualification of baseline low-temperature (180°C) a-Si:H process on the 6-in. line with rigid substrates, to transferring the process to flexible plastic and flexible stainless-steel substrates, to form factor scale-up of the TFT arrays, and finally manufacturing scale-up to a Gen 2 (370 × 470 mm) display-scale pilot line, will be reviewed.

Circuit-Level Impact of a-Si:H Thin-Film-Transistor Degradation Effects

This paper reviews amorphous silicon thin-film-transistor (TFT) degradation with electrical stress, examining the implications for various types of circuitry. Experimental measurements on active-matrix backplanes, integrated a-Si:H column drivers, and a-Si:H digital circuitry are performed. Circuit modeling that enables the prediction of complex-circuit degradation is described. The similarity of degradation in amorphous silicon to negative bias temperature instability in crystalline PMOS FETs is discussed as well as approaches in reducing the TFT degradation effects. Experimental electrical-stress-induced degradation results in controlled humidity environments are also presented.

Ultrathin Polymer Films for Microlithography

Ultrathin (14–22 nm) poly(methylmethacrylate) (PMMA) films prepared by both spin casting and Langmuir–Blodgett (LB) techniques and novolac films prepared by spin casting have been explored as high‐resolution electron beam resists. One‐eighth micron lines‐and‐spaces patterns (equal to the smallest beam diameter available) have been achieved by using a Perkin Elmer MEBES I pattern generation system as the exposure tool, and the definition of 45‐nm features has recently been achieved by using a high‐resolution electron beam lithography system. [J. H. Newman, K. E. Williams, and R. F. W. Pease, J. Vac. Sci. Technol. B 5, 88 (1987)]. The etch resistance of such films is sufficiently good to allow patterning of a chromium film suitable for photomask fabrication. The most surprising result has been that the pinhole densities in 14.3‐nm LB PMMA film and 22‐nm spin‐cast novolac film are only a few per cm2, considerably lower than the density in spin‐cast PMMA films of comparable thicknesses.

Observation of electron resonant tunneling in a lateral dual-gate resonant tunneling field-effect transistor

A new lateral resonant tunneling field‐effect transistor (LARTFET) has been fabricated using molecular beam epitaxy and ultrahigh‐resolution electron beam lithography. The LARTFET has two 80‐nm‐long gate electrodes separated by 100 nm. The dual gates create double potential barriers in the channel and a quantum well in between. Conductance oscillations are observed, which, for the first time, indicate electron resonant tunneling through the energy states in a lateral double‐barrier quantum well formed electrostatically. Furthermore, after illumination, two additional negative transconductance peaks are observed. These additional peaks may be related to electron resonant tunneling through the donor‐related deep levels in silicon‐doped Al0.35Ga0.65As .

Direct nanometer scale patterning of SiO2 with electron‐beam irradiation

Nanometer scale patterns have been fabricated in SiO2 by direct electron‐beam exposure. Two techniques have been developed to eliminate the surface contamination and enable the subsequent development of the patterns in HF based wet etches: (1) exposing the oxide through a sacrificial layer (previously reported) and (2) O2 reactive ion etching (RIE). The latter approach eliminates the need for a sacrificial layer and improves resolution by reducing the forward scattering of the beam. To determine the resolution of this process, patterns were fabricated with both 50‐ and 300‐kV electrons in thin SiO2 membrane samples and imaged in transmission. Transmission imaging avoids the resolution limit of secondary electron micrographs set by the lateral range of secondary electrons. At 300 keV with a line dose of 7.5 μC/cm, arrays of lines with a period down to 15 nm were achieved as opposed to the 21‐nm period previously reported using a sacrificial layer and secondary electron imaging of bulk substrates. A better ...

Stability of IZO and a-Si:H TFTs Processed at Low Temperature (200

Mixed-oxide thin-film transistors (TFTs) have been extensively researched due to their improved stability under electrical bias stress compared to amorphous-silicon TFTs. However, there are many challenges before they can reach the manufacturing stage. At the Flexible Display Center (FDC), Arizona State University, Tempe, we are developing a low temperature indium-zinc-oxide (IZO) TFT process suitable for flexible substrates such as polyethylene naphthalate (PEN). We report the effect of bias stress on the performance of these IZO TFTs and compare it with a-Si:H TFTs. We also report the design and fabrication of a 3.8-in QVGA electrophoretic display on PEN substrate using IZO TFT backplane.