Anil Ranjan Saha

Implementation of a heuristic method for standard cell placement

The implementation is described of a heuristic algorithm for the constructive placement of standard cells. In the first part of this algorithm, the whole interconnection network is partitioned into two parts using the mincut algorithm. In the second part, cells are assigned in rows such that the number of feedthroughs is minimal. In the third part, the position of the cell within each row is determined so that channel density is minimized. The time complexity of each iteration of the first part is linear in the size of the network; that of second part is O( c) where c is the number of cells and that of the third part is O( c x n) where n is the average number of cells in a row. The placement completion times obtained for several example circuits by implementing the algorithms in the language C on a UNIX machine are found to be significantly faster than those found by using SPAR, a conventional CAD placement tool based on mincut and simulated annealing.

Transistor Beta-phase-shift Oscillator†

ABSTRACT A new junction-transistor oscillator circuit is described. It makes use of the internal phase-shift of a transistor and only a single C-R section as the external phase-shifting network—advantage being taken of the low-input impedance of a common emitter junction transistor. Analytic expressions for the frequency of oscillation and minimum voltage feedback factor for sustained oscillations have been deduced. Calculated values of frequency and minimum voltage feedback factor are shown to compare favourably with the experimental values. A range of oscillation frequency extending to several times the cut-off value of the transistor is shown to be obtainable.

Some Algorithmic Improvements in Multi-Level Logic Minimisation

In this paper an improved method for extraction of common subfunction in Multilevel Logic Minimization is implemented. The method for extraction of subfunction of Mathony and Baitinger is modified here by using some heuristics. Firstly the literals are sorted in decreasing order of their weight instead of increasing order of their frequencies. Secondly, for finding factor of a hyperfunction, common output literal is not needed to be present. Thus a method is implemented which is more general in the sense that it can give solution for different kinds of circuits and more efficient in the sense that it uses less number of iteration passes to give the solutions. The method for extraction of common factors is also implemented. The time complexity for these two methods are compared. Then the two multi-level circuits obtained from the above two methods are compared with the circuit obtained from two-level minimization using VLSI package VINYAS-GX. For smaller two-level circuit, each method realises multilevel c...

An efficient ASIC solution for measurement of telephone dial test parameters

A new architecture and innovative logic designs are presented for miniature low-power hand-held telephone dial tester for implementation on a 3 μm CMOS gate array. It is an all digital ASIC hardware containing 2012 two-input equivalent NAND gates and a power dissipation of 150 microwatts at the operating frequency of 2 kHz and 5 V supply voltage.

A single-phase two frequency clocking scheme for race-free glitch-free outputs of synchronous digital systems

A new clocking scheme is developed to produce race-free, glitch-free outputs of synchronous digital systems. The maximum input clock frequency for race-free operation is calculated as a single-phase system. Output signals are sampled at twice the input clock frequency, at time instants when the glitches are not there. Using the scheme, glitches generated anywhere within a quarter (T/4) of the input clock period (T) can be eliminated. The margin T/4 is large enough for most practical systems. Hence the scheme is of universal application as verified by the simulation of two 3 μm CMOS gate array ASICs, designed using VINYAS CAD tools.

A Widely Programmable Multiply/Divide Digital Delay Line

A new programmable Multiply/Divide Digital Delay Line circuit is proposed and CIF obtained for the layout design of the delay line chip with 3μ CMOS standard cells. The chip is designed to control the delay of a 4 bit data word with 4 bit wide multiply programme word P and 8 bit wide devide programme word Q. The circuit is suited to low frequency operation and large delay generation. With a basic crystal frequency of 4 MHz, the circuit can be programmed to produce delays ranging from 0.06425 milli second to 139.264 milli second. Such a delay line chip may find wide application in factory automation, office automation and process industries. The complexity of the delay line chip is equivalent to 1348 two input NAND gates. After final placement and routing the chip size is 6782μ * 5898μ and estimated power dissipation is 9.7607 mW for a 5 volt power supply.

A Linear Frequency to Code Converter

Theory and operation of a novel phase-locked tracking type frequency to Code Converter (fDC) is described in this paper. Ingenious subcircuits have been developed and incorporated around the basic system to achieve speed-up, linearity and stability of conversion. Measurements on a prototype built with a few off-the-shelf TTL ICs confirmed the results of theoretical analysis. With a 10-MHz clock and a speed-up factor of 16, the conversion time is about 0.4 ms plus one period of the input Hertz for 8 bit resolution and about 100 ms plus one period of the input Hertz for 12 bit resolution. Small signal tracking time is only a fraction of the conversion time, the multiplying fraction being equal to the f-m index of the input Hertz. The system is characterized by very high resolution capability (at the cost of speed), high stability and true linearity with no offset error.

A Transistor Oscillator having Output Frequency Proportional to the D.C Supply Voltage

ABSTRACT The paper discusses a modified transistor beta-phase-shift oscillator and deduces the conditions under which the frequency may be made to vary linearly with supply voltage. A practical oscillator circuit based on these deductions is described. Forward biased p-n junctions in the collector load are used to compensate for variation of gain with supply voltage. The oscillator has a frequency shift of about 3.5 kc/s per volt of supply voltage. Possible application of the oscillator may be found as a wide deviation subcarrier FM oscillator in telemetry practices.

A New Design of μ-255/A-87. 56 CODEC Chip for Implementation with Gate Array

Nonlinear μ-law/A-law compandings are usually realized in CODEC chips through nonlinear amplification and uniform quantization or nonuniform quantization with ROMs. In this paper, we present a new design using random logic of several MSI subfunctions, so interconnected as to realize μ-255 CODEC operation when the control input μ/A = 1 and A-87.56 CODEC operation when the control input μ/A = 0. Two-phase clocks φ1and φ2 are used for encoding and decoding respectively. For a given control input, encoding or compression operation is performed during φ1 and decoding or decompression is performed during φ2. An innovative partitioning of the system function into appropriate subfunctions drastically reduces the gate count and power dissipation compared to the usual ROM implementation. Complete design of the chip from schematic capture of fabrication ready CIF of the layout design is described in the text. The chip contains 1276 equivalent two input NAND gates and has a pin count of 30. It is estimated that the power dissipation of the chip will be 58.27 milliwatts at an operating frequency of 1 MHz and power supply of 5 Volts.

Placement of Standard Cells by Multiple—Way Partitioning

In this paper an algorithm for multiple way network partitioning is developed extending the idea of two-way partitioning. Multi-level gain concept is adopted in this algorithm. Results from several examples run agree with the fact that direct r-way partitioning gives rise to lower cutset than hierarchical partitioning. This multi-way partitioning approach is used for Standard cell placement, such that each partition corresponds to each row of a Standard cell based chip. Finally successive rows of cells for placement are found such that number of vias is minimised. Experimental results of several placement problems show that the approach is both effective and efficient in yielding smaller cutset and hence better placement.