Bivas Dam

Optimal design of linear phase multi-band stop filters using improved cuckoo search particle swarm optimization

Optimal LPMBSF design using ICSPSO algorithm.Display Omitted The article represents the application of swarm and evolutionary method of design of three different types of digital linear phase multiband stop filters (LPMBSFs).Two proposed meta-heuristic hybrid algorithms called cuckoo search particle swarm optimization (CSPSO) and improved CSPSO (ICSPSO) algorithms are employed for the successful design of these LPMBSFs.The proposed ICSPSO algorithm is developed combining the advantage of cuckoo search algorithm into particle swarm optimization (PSO) and its group searching capability is enhanced, tuning the mutation operator of differential evolution (DE) algorithm. Filtering and design of suitable filters are the basic requirement in most of modern signal processing networks. In this manuscript, linear phase multiband stop filters (LPMBSFs) are designed using a robust hybrid metaheuristic algorithm called improved cuckoo search particle swarm optimization (ICSPSO) for searching desired impulse responses of the filters. Generally LPMBSFs are considered for simultaneous processing of group of spectra widely used in digital communication and signal processing applications. The window method and the simple frequency sampling method of designing linear phase multiband filters (LPMBFs) have no precise control over the stop band and pass band cut-off frequencies. Thus in order to improve the design strategy of the LPMBSF, optimum design criterion is devised where the error between ideal frequency response and practical frequency response is reduced by incorporating the efficient modern swarm and global evolutionary computation technique. The ICSPSO technique is such an excellent hybrid global random search technique for error minimization, and is structured incorporating the advantages of cuckoo search algorithm into particle swarm optimization (PSO) while the global searching capability is further accelerated by tuning the mutation operation of differential evolution (DE) technique. The quality of the proposed ICSPSO based filter design has been compared with other prominent optimal method of design such as hybrid cuckoo search particle swarm optimization (CSPSO), improved cuckoo search (ICS) optimization, and PSO.

A novel FPGA-based LVDT signal conditioner

This paper presents a phase compensated novel signal conditioner for a linear variable differential transformer (LVDT) and its FPGA based implementation. The LVDT output signal is a double-sideband suppressed-carrier amplitude-modulated (DSB-SC-AM) waveform, where the LVDT sinusoidal excitation is the carrier signal and the LVDT core position is the modulating signal. The proposed signal conditioner locates the carrier peaks in the LVDT output signal and provides a direct digital demodulation of the same at the said instants. Since the carrier component at the sampling instants equals the carrier amplitude, a simple gain scaling converts the read data to the LVDT core position measurement. The peak sensitive demodulation is insensitive to sensor induced phase lag and does not require external phase compensation network. This conditioner has better dynamic response than existing LVDT signal conditioners. Its overall error figures are also comparable with those of the existing solutions.

Design of multipurpose digital FIR double-band filter using hybrid firefly differential evolution algorithm

Abstract Signal filtering can be treated as one of the basic requisite of communication networks. Design of an appropriate digital filter demands such filter coefficients that will create the desired frequency response with tolerable amount of ripples in the stop band(s) and pass band(s) along with high attenuation in the stop band(s). Now-a-days, artificial evolutionary methods are employed in the modern digital filter design due to lots of advantages over typical methods. In this paper, multipurpose digital linear phase double band filter (LPDBF) is designed proposing a hybrid meta-heuristic technique called hybrid firefly differential evolution (HFDE) algorithm. Generally these filters are required in different specific modern digital system networks for the simultaneous processing of signals present in two or three different channels. The proposed HFDE is an efficient evolutionary hybrid technique and is modelled considering both the optimization advantages of improved differential evolution (IDE) and firefly techniques. The global searching capability of IDE technique is strengthened by improved firefly movement. The performance of the proposed HFDE method of LPDBF design is contrasted with few popular optimal methods of design.

An in situ trap capacitance measurement and ion-trapping detection scheme for a Penning ion trap facility

This paper presents the design and implementation of an in situ measurement setup for the capacitance of a five electrode Penning ion trap (PIT) facility at room temperature. For implementing a high Q resonant circuit for the detection of trapped electrons/ions in a PIT, the value of the capacitance of the trap assembly is of prime importance. A tunable Colpitts oscillator followed by a unity gain buffer and a low pass filter is designed and successfully implemented for a two-fold purpose: in situ measurement of the trap capacitance when the electric and magnetic fields are turned off and also providing RF power at the desired frequency to the PIT for exciting the trapped ions and subsequent detection. The setup is tested for the in situ measurement of trap capacitance at room temperature and the results are found to comply with those obtained from measurements using a high Q parallel resonant circuit setup driven by a standard RF signal generator. The Colpitts oscillator is also tested successfully for supplying RF power to the high Q resonant circuit, which is required for the detection of trapped electrons/ions.

An FPGA-based integrated signal conditioner for measurement of position, velocity and acceleration of a rotating shaft using an incremental encoder

Digital motion control applications, where electric motors are utilized as actuators, use incremental encoders as feedback devices to sense the rotating shaft position. However, for the controller to implement an accurate tracking of input position or velocity trajectories, and to make the tracking performance robust with respect to unpredictable disturbances like parameter uncertainties and load fluctuations, measurement of velocity and acceleration data is also required. In majority of the existing digital motion control solutions, direct measurement of velocity and acceleration is rarely done. Instead, they are estimated from the discrete position data obtained from the incremental encoder. Well documented velocity and acceleration estimation algorithms exist, and the literature report both simulation and experimental results on the performance of the said algorithms with typical input position trajectories. However, no integral hardware module that uses an incremental encoder to provide position, velocity and acceleration measurement is reported. This paper presents the design and FPGA-based implementation of an integrated signal conditioner that uses the signals coming from an incremental encoder to measure the current position, and then estimate the current velocity and acceleration from it, and its performance on a test-rig. With a fast, industry-standard serial link, the proposed signal conditioner qualifies to be an integrated feedback device in digital motion control applications.

A carrier peak synchronous direct digital demodulation technique and its FPGA implementation

Abstract This paper presents a carrier peak synchronous direct digital demodulation scheme for linear modulated signals and its innovative FPGA implementation. The demodulation scheme generates a carrier equivalent signal that is in quadrature with the modulated signal and strobes the modulated signal at the carrier peaks. A digitizer in the form of an analog to digital converter now converts the sampled data to a digital count, thereby producing a direct digital read-out of the modulated signal. This obviously eliminates the necessity of the standard sequence of multiplication, low pass filtering and subsequent processing common in existing analog and digital synchronous quadrature demodulators. Removal of the low pass filtering stage eliminates the inherent filter time lag that proves beneficial in those measurement applications where exact phase sensitive detection of the measurand at specific time instant is important. The feasibility of the proposed scheme is established through its FPGA implementation for reconstructing the modulating signal by sampling the modulated signal at every carrier peak and holding the sampled value till the next sampling instant. The implementation is found to automatically capture and remain tuned to any carrier frequency in the range 763 Hz to 100 kHz.

An efficient ASIC solution for measurement of telephone dial test parameters

A new architecture and innovative logic designs are presented for miniature low-power hand-held telephone dial tester for implementation on a 3 μm CMOS gate array. It is an all digital ASIC hardware containing 2012 two-input equivalent NAND gates and a power dissipation of 150 microwatts at the operating frequency of 2 kHz and 5 V supply voltage.

A single-phase two frequency clocking scheme for race-free glitch-free outputs of synchronous digital systems

A new clocking scheme is developed to produce race-free, glitch-free outputs of synchronous digital systems. The maximum input clock frequency for race-free operation is calculated as a single-phase system. Output signals are sampled at twice the input clock frequency, at time instants when the glitches are not there. Using the scheme, glitches generated anywhere within a quarter (T/4) of the input clock period (T) can be eliminated. The margin T/4 is large enough for most practical systems. Hence the scheme is of universal application as verified by the simulation of two 3 μm CMOS gate array ASICs, designed using VINYAS CAD tools.

A Widely Programmable Multiply/Divide Digital Delay Line

A new programmable Multiply/Divide Digital Delay Line circuit is proposed and CIF obtained for the layout design of the delay line chip with 3μ CMOS standard cells. The chip is designed to control the delay of a 4 bit data word with 4 bit wide multiply programme word P and 8 bit wide devide programme word Q. The circuit is suited to low frequency operation and large delay generation. With a basic crystal frequency of 4 MHz, the circuit can be programmed to produce delays ranging from 0.06425 milli second to 139.264 milli second. Such a delay line chip may find wide application in factory automation, office automation and process industries. The complexity of the delay line chip is equivalent to 1348 two input NAND gates. After final placement and routing the chip size is 6782μ * 5898μ and estimated power dissipation is 9.7607 mW for a 5 volt power supply.

Design of Linear Phase Band Stop Filter Using Fusion Based DEPSO Algorithm

This manuscript prepares a modern hybrid technique by combining the usual particle swarm optimization (PSO) technique with differential evolution (DE) technique, named as fusion based differential evolution particle swarm optimization (DEPSO) in order to enhance the global search abilities, while solving impulse response of linear phase digital band stop filter. The linear phase band stop filter is mostly considered as a nonlinear multimodal problem. The DEPSO is a heuristic based global search method modelled on considering the advantages of both of the methods to enhance the superiority of result and convergence speed. The performance of the intended DEPSO based approach has been contrasted with few renowned optimization techniques such as PSO, comprehensive learning PSO (CLPSO), craziness based PSO (CRPSO) and DE. The proposed DEPSO based result confirms the supremacy of solving design problems of FIR filters.