Anil S. Keshavamurthy

System software for persistent memory

Emerging byte-addressable, non-volatile memory technologies offer performance within an order of magnitude of DRAM, prompting their inclusion in the processor memory subsystem. However, such load/store accessible Persistent Memory (PM) has implications on system design, both hardware and software. In this paper, we explore system software support to enable low-overhead PM access by new and legacy applications. To this end, we implement PMFS, a light-weight POSIX file system that exploits PMs byte-addressability to avoid overheads of block-oriented storage and enable direct PM access by applications (with memory-mapped I/O). PMFS exploits the processors paging and memory ordering features for optimizations such as fine-grained logging (for consistency) and transparent large page support (for faster memory-mapped I/O). To provide strong consistency guarantees, PMFS requires only a simple hardware primitive that provides software enforceable guarantees of durability and ordering of stores to PM. Finally, PMFS uses the processors existing features to protect PM from stray writes, thereby improving reliability. Using a hardware emulator, we evaluate PMFSs performance with several workloads over a range of PM performance characteristics. PMFS shows significant (up to an order of magnitude) gains over traditional file systems (such as ext4) on a RAMDISK-like PM block device, demonstrating the benefits of optimizing system software for PM.

Autonomous learning approach to characterizing motion behavior

Unattended falls can lead to serious medical issues among the elderly, especially when motor functions may become inactive. Motion sensors like accelerometer can aid in automatic characterization and classification of human motion. Un-Classified motion can be accounted for anomaly that when reported to the online knowledge builder can correct the existing model or estimate additional classes into that model. In this paper we develop an alert system using low power Intel Quark D1000 MCU that characterizes the motion behavior using Logistic Model Trees (LMT) and estimates an anomaly in motion behavior while augmenting the model using online learning. The goal is to build a useability model where an unclassified behavior (corresponding to accelerometer data) can be logged and upon additional intervention can be re-evaluated for re-classification. This will lead to autodetecting un-desired motion activities (like falls) and avoid false positives to activities of daily life.

Autonomic tool for optimal cache-sharing using evolutionary techniques

Chip multiprocessors are subject to performance degradation due to inefficient cache management. Conventional cache distribution schemes treat all cores equally, leading to cache-contention issues caused by thrashing behaviors. This paper presents an automation tool that ensures optimal cache-sharing amongst cores executing workloads concurrently and competing for cache resources. We demonstrate that dynamic cache partitioning among selected cores improves overall performance. Our automation tool uses CPU performance counters that feed into a genetic algorithm to ensure optimal cache distribution. This scheme minimizes the overall LLC miss rate by 12.879% and increases the overall IPC by 2.426% over the conventional cache partitioning.

Minimalist Design for Accelerating Convolutional Neural Networks for Low-End FPGA Platforms

Deep neural networks have gained tremendous attention in both the academic and industrial communities due to their performance in many artificial intelligence applications, particularly in computer vision. However, these algorithms are known to be computationally very demanding for both scoring and model learning applications. State-of-the-art recognition models use tens of millions of parameters and have significant memory and computational requirements. These requirements have restricted the users of deep neural network applications to high-end, expensive, and power hungry IoT platforms to penetrate the deep learning markets. This paper presents work at the leading edge intersection of several evolving technologies, including emerging IoT platforms, Deep Learning, and Field-programmable Gate Array (FPGA) computing. We demonstrate a new minimalist design methodology that minimizes the utilization of FPGA resources and can run deep learning algorithms with over 60 million parameters. This makes particularly suitable for resource-constrained, low-end FPGA platforms.

Deep learning with ensemble classification method for sensor sampling decisions

Modern mobile pervasive applications focus on context awareness that monitors a diverse range of personal domains. In order to infer contextual information, most of these applications require the collection of raw data from sensors which are either embedded in personal smartphones or worn by the user. Critical context-aware applications rely on continuous accurate monitoring of the users current context. Continuous sensing mechanisms in sensors cost high energy consumption to support accurate contextual detection. Hence, there is a trade-off between the classification accuracy and the energy consumption. In this paper, we exploit the advantages of Deep Neural Network (DNN) with ensemble classification of other complementary machine learning approaches to determine the best sensor sampling frequency for the recognition of a given context. DNN relies on raw data for classification while the other complementary methods (such as Decision Tree and Naïve Bayes) use feature recognition to classify data. Therefore, our approach provides a range of granularity from raw data. We prove the robustness of our approach in experiments which show high accuracy in context recognition. In addition, real experiments demonstrate the energy gains of the proposed algorithm which reach 87% reduction in energy consumption when compared to continuous sensing.