Anis Uzzaman

Not all Delay Tests Are the Same - SDQL Model Shows True-Time

Assessing the effectiveness of transition fault testing by the test coverage is misleading and can result on lower product quality. In reality, the actual timing of the test for each fault determines if a delay defect of a given size is detected or not. Transition tests that use actual circuit timings to create tests with the tightest possible timing detect more defects and have higher test effectiveness for a given test coverage. This paper validates this assertion using a statistical delay quality model (SDQM) model to estimate the statistical delay quality level (SDQL) of several chips. The comparison includes transition tests generated with and without actual circuit timing as a function of the actual timing of the tests for each fault

Using Programmable On-Product Clock Generation (OPCG) for Delay Test

On-product clock generation (OPCG) has been used for many years, often in conjunction with logic and memory BIST, but it is a labor-intensive process to identify the cut- points and the OPCG behavior so the ATPG tools can ignore the OPCG logic. Supporting programmable OPCG logic in an ASIC methodology flow required us to automate the OPCG test generation flow. This paper describes how we provide a means for dealing with the programmable aspects of OPCG for use during ATPG and show some results for a few real designs.

Low Cost Delay Testing of Nanometer SoCs Using On-Chip Clocking and Test Compression

Testing at-speed delay defects is difficult on a speed constrained low cost tester. This paper describes the use of a clock chopper based onproduct clocking circuitry and interfaces to delay ATPG to achieve reliable test patterns. We also describe the test compression methods used to address the problem of increased test data volume due to delay tests. Data is presented on several industrial circuits to demonstrate the effectiveness of these DFT methods on nanometer designs. Our results show that a seamless combination of atspeed delay testing with compression can help to test the nanometer defects at a very competitive cost.

Why is Conventional ATPG Not Sufficient for Advanced Low Power Designs

Designs using advanced low power techniques like Multi- Supply Multi-Voltage and Power Shutoff bring with them a new set of challenges that manufacturing test must deal with carefully. These designs have low power components – isolation cells, retention flops, level shifters, power switches, etc., – that must be tested not only structurally but also addressing their behavior across multiple power modes. This paper describes the challenges in testing the key low power components and proposes novel solutions. The defective behavior of state retention logic is modeled to enable fault grading. ATPG modeling of defective behavior of isolation logic and level shifters is described for designs that support multiple supply voltages and power shutoff. The solutions are supported by experimental results on industrial designs.

Automated handling of programmable on-product clock generation (OPCG) circuitry for delay test vector generation

Although on-product clock generation (OPCG) has been used for many years, often in conjunction with logic and memory BIST, it has usually been a very manual process to identify the cut-points and the OPCG behavior to ATPG tools so they can avoid dealing directly with the OPCG logic. To support programmable OPCG logic in an ASIC methodology flow required us to find a way to automate the handling of the OPCG logic and the various clocking sequences it can produce. This paper describes how we provide a means for dealing with the programmable aspects of OPCG for use during ATPG and shows some results.

A Review of Power Strategies for DFT and ATPG

This paper presents a review of power topics for DFT and ATPG. The issue of increasing power in ASIC design is an important topic.in terms of power management and CMOS power consumption has been considered as low-power. The related issues of power and test have been discussed, but often in the fairly narrow context of limiting power during scan test. This topic is becoming increasingly important as power management strategies within chips become more common and complex and at-speed test becomes more important for detecting defects which escape the classical stuck-at model. Increasingly chips incorporate features to allow active power management.

Early Life Cycle Yield Learning for Nanometer Devices Using Volume Yield Diagnostics Analysis

As the industry fabricates devices with more on-chip circuitry using complex, advanced process technologies, the challenge to achieve satisfactory yield becomes more daunting (Madge, 2005). Leading-edge nanometer designs can be sensitive to inherent irregularity in sub-wavelength photolithography and variability in parametric characteristics often found in nanometer manufacturing environments. These factors often result in devices being fabricated with intermittent electrical performance problems. These types of systemic interactions (process-design) are the major factor in manufacturing yield loss in nanometer technology nodes. Failure diagnostics is being asked to identify these systemic defects, preferably during early product development, and provide enough information so that each defect is understood and can be addressed. This paper presents a case study, which empirically examines the challenges of achieving high yield during the early stage of wafer production with an examination of yield loss mechanisms. A proven methodology and model (volume yield diagnostics) for an economic justification enabling the timely identification of yield loss is discussed along with quick process methodology and analysis results based on real manufacturing data

Automatic Handling of Programmable On-Product Clock Generation (OPCG) Circuitry for Low Power Aware Delay Test

This paper describes how we provide a mean for dealing with the programmable aspects of on-product clock generation (OPCG) for use during ATPG and how that can also help with low power delay test. The system described in this paper automatically generates mode initialization sequence, setup sequence, test sequence and others and enables low power aware delay test when faster on product clocks are present on board. This system has successfully been used to process delay test for ASIC chips even with 22 PLLs on board.

Practical Aspects of Delay Testing for Nanometer Chips

As SoC feature sizes are moving down to the nanometer range there is an increasing need to develop high quality, cost-effective and sensitive tests for nanometer devices. Many of the newer defects like resistive vias and bridges exhibit defective timing behavior, and require the usage of the transition fault model and sophisticated control of the launch-to-capture timings to the equivalent of system speeds.

Is Low Power Testing Necessary? What does the Test Industry Truly Need?

With the changing face of the consumer driven semiconductor industry, there are new challenges facing the industry which need to be resolved. Minimizing Power dissipation is a significant and growing challenge with the growth of the wireless and portable device segments and with the need to be ‘green’. Even during manufacturing test, power is definitely among the top ten items needing attention and expertise. Since 90-nm there has been a recognition that power consumption during test can be a factor affecting product quality and yield. Excessive power consumption during manufacturing test affects the reliability of digital integrated circuits, leading to power-driven failures and higher infant mortality. These trends if continuing on their present course will force designers to adopt specific power management and low power design techniques for manufacturing test.