Brian Foutz

Channel masking synthesis for efficient on-chip test compression

The effectiveness of on-product test compression methods is degraded by the capture of unknown logic states (X-states) by the scan elements. This work describes a simple but cost-effective solution called channel masking that masks the X-states and allows test compression methods to be widely deployed on a variety of designs. It also discusses various aspects of the channel masking hardware and the synthesis and validation methodology to support its use in a typical design flow. Results are presented to show its effectiveness on some large industrial designs.

Efficient testing of hierarchical core-based SOCs

As chip design sizes continue to increase and they contain multiple instances of large and small cores, there is a need for a chip test architecture that allows efficient chip-level tests to be created while also reducing the memory and CPU time needed to create the tests. We define a hierarchical and core-based architecture for generating tests for cores and migrating them to the chip. This architecture allows testing multiple instances of the same core for the same cost as testing a single instance. The architecture also allows testing multiple instances of different cores as well. Memory use is kept low by generating tests for cores out of context and migrating them to the chip. We never have to build a full gate-level chip ATPG model. We show results of pattern count reduction possible when targeting multiple cores simultaneously.

Low cost at-speed testing using On-Product Clock Generation compatible with test compression

At-speed testing with functional speed clocks is often done using On-Product Clock Generation (OPCG). When test compression logic is also embedded within the circuits DFT architecture, the loading of the OPCG programming bits can impact test compression results. We present an approach to the use of OPCG that enables high-speed testing and is compatible with test compression. It also enables the use of tests that pulse multiple domains to further reduce test time and data volume. It also supports generation of inter-domain and static ATPG tests. We present results on four designs; one design shows an over 35% reduction in patterns due to use of multiple clock domains per test. An additional 10+% savings is possible using side-scan to load the OPCG programming registers.

Automation of IEEE 1149.6 Boundary Scan Synthesis in an ASIC Methodology

This paper describes an automated methodology to insert IEEE 1149.6 boundary scan in a production ASIC environment. The methodology includes updating the ASIC library to support the new test receiver component, updating the TAP controller logic and boundary cells, and finally providing support for embedded high speed I/O logic. Results from several industrial designs and example circuits are shown. These examples include multi-GHz serial I/O such as those used with serial ATA and PCI-Express

Optimizing Test Data Volume Using Hybrid Compression

This paper describes a simple means to enable direct diagnosis by bypassing MISRs on a small set of tests while achieving ultimate output compression using MISRs for the majority of tests. By combining two compression schemes, XOR and MISRs in the same device, it becomes possible to have high compression and still support volume diagnostics.

Low Power Reduced Pin Count Test Methodology

This paper explores the savings in power achieved using an I/O gating and Reduced Pin Count Test (RPCT) technique during manufacturing test. Since I/O pads consume significant power, preventing them from toggling during test will bring about a corresponding savings in power. The paper describes a fully automated RPCT methodology for low power that includes insertion of the RPCT and I/O gating logic and test generation. Based on simulation of the ATPG patterns, we show that the power consumed during scan test can be reduced significantly.