Anita Tino

Multi-objective Tabu Search based topology generation technique for application-specific Network-on-Chip architectures

This paper presents a power and performance multi-objective Tabu Search based technique for designing application-specific Network-on-Chip architectures. The topology generation approach uses an automated technique to incorporate floorplan information and attain accurate values for wirelength and area. The method also takes dynamic effects such as contention into account, allowing performance constraints to be incorporated during topology synthesis. A new method for contention analysis is presented in this work which makes use of power and performance objectives using a Layered Queuing Network (LQN) contention model. The contention model is able to analyze rendezvous interactions between NoC components and alleviate potential bottleneck points within the system. Several experiments are conducted on various SoC benchmark applications and compared to previous works.

Synthesis of NoC Interconnects for Custom MPSoC Architectures

As technology continues to demand high performance, low power, and integration density, NoC system designers consider multiple aspects during the design phase. This paper addresses these issues and presents an NoC design methodology for generating high quality interconnects for custom Multiprocessor System-on-Chip (MPSoC) architectures. Our design methodology incorporates the main objectives of power and performance during topology synthesis while employing both analytical and simulation based automated techniques. A rendezvous interaction performance analysis method is presented where Layered Queuing Network models are invoked to observe the asynchronous interactions between NoC components and identify possible performance degradation in the on-chip network. Several experiments are conducted using various SoC benchmark applications to compare the power and performance outcomes of our proposed technique.

Power and Performance Tabu Search Based Multicore Network-on-Chip Design

This paper presents a Tabu search based approach for the topology synthesis of application-specific multicore architectures using an automated design technique. The Tabu search method incorporates multiple objectives in order to generate an optimal NoC topology which accounts for both power and performance factors. The method generates a system-level floorplan in each major stage of the topology synthesis. By incorporating the floorplan information, it is possible to attain accurate values for power consumption of the routers and physical links, as well as manage the interconnections within the system. The technique also includes a contention analyzer that assesses performance and omits any potential bottlenecks. The contention analyzer uses a Layered Queuing Network approach to model the rendezvous interactions amongst system components. Several experiments are conducted using various SoC benchmark applications to compare the power and performance outcomes of the proposed technique.

Wireless vibrotactile feedback system for postural response improvement

This paper presents an evaluation of a real-time wireless body sensor network for the improvement of postural balance response. The system senses body sway using accelerometers and provides vibrotactile feedback to multiple points on the inner forearm, allowing the subject to obtain a clear indication of imbalanced movements within their center of gravity and respective surroundings. The wireless body sensor network is ergonomic, allowing the subject to feel comfortable and experience unconfined movements during its use. The system transmits realtime data to a local host computer, where the data is recorded and displayed graphically. This recorded data monitors the subjects progress and allows any sudden falling movements to be overseen by care-givers. Pilot data measuring postural responses to perturbations with and without the system are conducted. Results obtained suggest that this system can improve postural responses, where it is demonstrated that such an intelligent and user-friendly system can be applied to rehabilitate the loss of balance in hospital and home-care patients.

Synthesis of NoC Interconnects for Multi-core Architectures

As SoC applications demand high performance and integration density, SoC designers consider multiple aspects during the design phase. This paper presents a Network-on-Chip (NoC) design methodology for generating high quality interconnects for multi-core System-on-Chip architectures. The design process incorporates the main objectives of low power and high performance during topology synthesis. A rendezvous interaction performance analysis method is presented where Layered Queuing Network models are invoked to observe the asynchronous interactions between NoC components and identify possible performance degradation within the on-chip multi-core network. Several experiments are conducted using various SoC benchmark applications to compare the power and performance outcomes of our proposed technique.

Assessing Multi-task Placement Algorithms in RCUs

In response to the current requirements of energy efficiency and high performance in computing systems, architects have turned towards customization. General purpose computing however remains a challenge as processors must adhere to a variety of applications, on-chip resources, and increased performance without solely relying on transistor scaling and additional cache levels. For this reason, the concept of Reconfigurable Computing Unit (RCU) processors have been proposed which redesign the conventional processor on the microarchitectural and architectural level. RCUs are extended in this work to support a multi-task workload using OmpSs, where task and instruction placement algorithms are thoroughly assessed for effects of performance and energy efficiency. Experimental results demonstrate that a single RCU processor with a double engine configuration is able to exceed single-core performance on average by 1.48x and achieve/exceed dual-core performance. The various inter-and intra-task placement algorithms tested also display up to 16.7% and 23% fluctuation in performance and energy efficiency, respectively, depending on the method and RCU engine combination employed.

Designing power and performance optimal application-specific Network-on-Chip architectures

Abstract This paper presents an optimal method for topology synthesis by taking into account factors related to power, performance, and contention in an application-specific Network-on-Chip (NoC) architecture. A Tabu search based approach is used for topology generation with an automated design technique, incorporating floorplan information to attain accurate values for power consumption of the routers and physical links. The Tabu search method incorporates multiple objectives and is able to generate optimal NoC topologies which account for both power and performance. The contention analysis technique assesses performance and relieves any potential bottlenecks using virtual channel insertion after considering its effect on power consumption and performance improvement within the NoC. The contention analyzer uses a Layered Queuing Network approach to model the rendezvous interactions among system components. Several experiments are conducted using various SoC benchmark applications to compare the power and performance outcomes of the proposed technique.

Towards Multicore Performance with Configurable Computing Units

Energy efficiency and the need for high performance has steered computing platforms toward customization. General purpose computing however remains a challenge as on-chip resources continue to increase with a limited performance improvement. In order to truly improve processor performance, a major reconsideration at the microarchitectural level must be sought with regards to the compiler, ISA, and general architecture without an explicit dependence on transistor scaling and increased cache levels. In attempts to assign the processor transistor budget towards engineering ingenuity, this paper presents the concept of Configurable Computing Units CCUs. CCUs are designed to make reconfigurability in general purpose computing a reality by introducing the concept of logical and physical compilation. This concept allows for both the application and underlying architecture to be considered during the compilation process. Experimental results demonstrate that a single CCU core consisting of double engines achieves dual core performance, with half the area and power consumption required of a conventional monolithic CPU.

Addressing processor back-end issues with RCUs

Traditional microprocessors have long benefited from the transistor density gains of Moores law. Diminishing transistor speeds and practical energy limits however have created new challenges in technology, where the exponential performance improvements we have been accustomed to from previous computing generations continue to slowly cease. These factors signify that while transistors continue to scale and other technological means are researched, the design challenges faced by computer architects will only be temporarily masked before similar challenges are yet again encountered. This work addresses several conventional processors back-end issues by introducing the concept of Reconfigurable Computing Units (RCUs). RCUs employ logical and physical compilation to maintain compatibility with current compilers and ISAs, while supporting an underlying reconfigurable processor architecture. RCUs consist of a variety of execution engines and functional units, connected through a configurable single-cycle multi-hop registerSwitch interconnect. Experimental results demonstrate that RCUs can achieve up to a 2× performance improvement in purely sequential applications with 3× less logic utilization than a conventional CPU back-end.

High performance NoC synthesis using analytical modeling and simulation with optimal power and minimal IC area

This paper presents an analytical modeling and simulation NoC synthesis tool for designing low-power, high performance MPSoCs. The design process employs a power and performance predictive analysis method to combine the advantages of modeling and simulation during NoC topology generation. The synthesis tool is able to accurately account for performance metrics of the target application, while simultaneously evaluating for power related constraints using a multi-objective Tabu search based method. The tool is also able to assess and alleviate dynamic effects of contention and deadlock during synthesis. The proposed design method was tested using various multimedia and networking benchmarks, where the generated topologies were found to offer improvements in power and performance when compared to existing works.