Gul N. Khan

Throughput-Oriented NoC Topology Generation and Analysis for High Performance SoCs

This paper presents a new approach to the design and analysis of NoC topologies which is based on the transaction-oriented communication methods of on-chip components. We propose two algorithms that attempt to meet the communication requirement of an on-chip application using a minimum number of network resources for the task, by generating application-specific topologies. In addition, to aid the design process of complex systems, the design method incorporates a form of predictive analysis which can estimate the degree of contention in a given system without performing detailed simulation. This predictive analysis method is used to determine the minimum frequency of operation for generated topologies, and is incorporated into the topology generation process. The proposed design method was tested using real-word applications, including an MPEG4 decoder and a multi-window display application. The generated topologies were found to offer similar or better performance when compared with regular topologies. However, the topologies generated by our method were more economical, using, on average, half the network resources of regular topologies.

Vision based navigation system for an endoscope

A vision based navigation system to guide an endoscope inside a human colon has been designed and tested. It uses low level vision techniques to extract two types of navigational landmarks, dark regions and curved contours. Dark regions correspond to the distant inner space of the colon, called the lumen. The curved contours represent occlusions due to the inner colon muscles. A hierarchical search space and environment representation, called the QL-tree, was developed to integrate the visual features and implement the navigation system. It uses multiple quadtrees which are linked at all hierarchical levels. A multiprocessor system was employed to achieve real-time performance. The endoscope navigation system has been used successfully in artificial colon models.

Secure authentication scheme for passive C1G2 RFID tags

Privacy and security concerns inhibit the fast adaption of RFID technology for many applications. A number of authentication protocols that address these concerns have been proposed but real-world solutions that are secure, maintain low communication cost and can be integrated into the ubiquitous EPCglobal Class 1 Generation 2 tag protocol (C1G2) are still needed and being investigated. We present a novel authentication protocol, which offers a high level of security through the combination of a random key scheme with a strong cryptography. The protocol is applicable to resource, power and computationally constraint platforms such as RFID tags. Our investigation shows that it can provide mutual authentication, untraceability, forward and backward security as well as resistance to replay, denial-ofth-service and man-in-the-middle attacks, while retaining a competitive communication cost. The protocol has been integrated into the EPCglobal C1G2 tag protocol, which assures low implementation cost. We also present a successful implementation of our protocol on real-world components such as the INTEL WISP UHF RFID tag and a C1G2 compliant reader.

Extracting contours by perceptual grouping

Abstract A new contour extraction method is described in this paper. It is based on organization of the image data using perceptual grouping rules, and is therefore largely domain independent. The first step is to form an intermediate line segment representation of the contours by grouping edge points in parallel and at different resolutions. The main feature of the line segment extraction process is the identification, by perceptual criteria, of weak but significant edge points for participation in the grouping process. In the second stage the line segments are grouped into contours, again on the basis of perceptual criteria. This grouping stage is carried out hierarchically using a pyramid structure. In both cases, the use of perceptual grouping allows the filtering of noisy edges and line segments regardless of their strength.

Efficient Dynamic Virtual Channel Organization and Architecture for NoC Systems

A growing number of processing cores on a chip require an efficient and scalable communication structure such as network on chip (NoC). The channel buffer organization of NoC uses virtual channels (VCs) to improve data flow and performance of the NoC system. Dynamically allocated multiqueues (DAMQs) are an effective mechanism to achieve VC flow control with maximum buffer utilization. In this model, VCs employ variable number of buffer slots depending on the traffic. Despite the performance merits of DAMQs, it has some limitations. We propose a new input-port microarchitecture to support our efficient dynamic VC (EDVC) approach that is built on DAMQ buffers. To demonstrate the advantages of EDVC, we compare its microarchitecture with that of the conventional dynamic VC (CDVC), which also employs link-list tables for buffer organization. In terms of hardware, EDVC input-port organization consumes on average 61% less power for application-specific integrated circuit design when compared with the CDVC input port. The saving is even better when compared with VC regulator methodology. An EDVC approach can improve NoC latency by 48%-50% and throughput by 100% on average as compared with the CDVC mechanism.

Secure RFID Authentication Protocol with Key Updating Technique

RFID systems are being used in various pervasive applications. Therefore, security and privacy protection is an important issue that needs to be addressed. In this paper, we present a secure mutual authentication protocol for RFID systems that is based on symmetric key technique with an efficient key updating mechanism. The objective is to improve the system security against replay, eavesdropping and man-in-the-middle attacks while maintaining lower computation, communication and storage. We also compare our authentication method with some recent protocols that deploy the same cipher (XTEA) by implementing the protocols on the same RF based system. Our proposed authentication protocol provides higher security level and lower computation and communication costs.

Multi-objective Tabu Search based topology generation technique for application-specific Network-on-Chip architectures

This paper presents a power and performance multi-objective Tabu Search based technique for designing application-specific Network-on-Chip architectures. The topology generation approach uses an automated technique to incorporate floorplan information and attain accurate values for wirelength and area. The method also takes dynamic effects such as contention into account, allowing performance constraints to be incorporated during topology synthesis. A new method for contention analysis is presented in this work which makes use of power and performance objectives using a Layered Queuing Network (LQN) contention model. The contention model is able to analyze rendezvous interactions between NoC components and alleviate potential bottleneck points within the system. Several experiments are conducted on various SoC benchmark applications and compared to previous works.

XTEA encryption based novel RFID security protocol

RFID technology has been widely used in logistic and authentication applications, but it still has many potential issues such as the risks of privacy and security. This paper presents a novel RFID security protocol based on the XTEA encryption. Analysis of the security and privacy of this novel protocol is performed using SystemC based modeling. Different attack models are implemented, and the results indicate that the protocol is robust and safe against major known attacks.

Secure Authentication Protocol for RFID Systems

Authentication of products and humans is one of the main applications of RFID technology. In this paper, we present a novel cryptographic authentication protocol that is fully secure and it fills the security holes imposed by RFID technology. Our proposed authentication protocol has a significantly lower cost in terms of computation, memory and communication as compared to most of the existing RFID protocols. We compare our protocol with the existing protocols by implementing all these authentication protocols first time on a passive, computation capable RFID tag developed by Intel known as WISP.

Flexible simulation and modeling for 2D topology NoC system design

Network on Chip (NoC) is a new paradigm that can solve the problems related to System on Chip (SoC) design. These problems and challenges become more significant when the complexity of SoC increases. The vast volume of these challenges requires a new and flexible NoC test framework (simulator) to be investigated. We have developed a general purpose SystemC based NoC simulator that employs some new approaches to have a superior test system as compared to the past NoC simulators. The simulator mainly target 2D regular NoC topologies where deterministic and adaptive routing techniques that play a key role in the NoC performance. Various NoC design parameters are analyzed by trading off throughputs and latencies. The results show that for some cases the new Line-Probe routing is faster and contention free for local traffic in Torus topology.