Ankit More

Simulation based study of on-chip antennas for a reconfigurable hybrid 3D wireless NoC

The feasibility of using on-chip antennas for a reconfigurable 3D wireless network-on-chip (3D-WiNoC) on a 3D integrated circuit (IC) is shown. The reconfigurable 3D-WiNoC is designed with on-chip antennas which are proposed to be used in conjunction with the metal interconnects making it a hybrid design. The feasibility of the on-chip antennas is shown by performing a 3-D finite element method (FEM) based full wave electro-magnetic analysis on a 3D IC model. The 3D IC is modeled according to a complimentary metal oxide semiconductor (CMOS) silicon on insulator (SoI) Benzocyclobutene (BCB) polymer adhesive bonding 3-D circuit integration technology. It is shown that it is possible to have two different frequency domains for the signal sources and the dynamic switching of the signal sinks between the two frequency domains, with minimal design and area overhead. When implemented, the proposed hybrid network architecture with two frequency channels can reduce the latency and increase the network throughput.

Synchrotrace: synchronization-aware architecture-agnostic traces for light-weight multicore simulation

Trace-driven simulation of chip multiprocessor (CMP) systems offers many advantages over execution-driven simulation, such as reducing simulation time and complexity, and allowing portability, and scalability. However, trace-based simulation approaches have encountered difficulty capturing and accurately replaying multi-threaded traces due to the inherent non-determinism in the execution of multi-threaded programs. In this work, we present SynchroTrace, a scalable, flexible, and accurate trace-based multi-threaded simulation methodology. The methodology captures synchronization- and dependency-aware, architecture-agnostic, multi-threaded traces and uses a replay mechanism that plays back these traces correctly. By recording synchronization events and dependencies in the traces, independent of the host architecture, the methodology is able to accurately model the non-determinism of multi-threaded programs for different platforms. We validate the SynchroTrace simulation flow by successfully achieving the equivalent results of a constraint-based design space exploration with the Gem5 Full-System simulator. The results from simulating benchmarks from PARSEC 2.1 and Splash-2 show that our trace-based approach with trace filtering has a peak speedup of up to 18.4x over simulation in Gem5 Full-System with an average of about 7.5x speedup. We are also able to compress traces up to 74% of their original size with almost no impact on accuracy.

Simulation based study of wireless RF interconnects for practical CMOs implementation

An electromagnetic analysis for the practical implementation of on-chip antennas to be used as wireless IC interconnects is presented. The undesired electromagnetic signal coupling between the on-chip antennas and the metal interconnects is characterized under varying geometries and placement of the metal interconnects. The variations in the transmission gain between the antenna pair due to the typical complementary metal oxide semiconductor (CMOS) manufacturing requirements are presented. Using a 3-D finite element method (FEM) based full wave electromagnetic solver, it is shown that the antenna characteristics are significantly impacted by the presence of the essential epitaxial layer and the required minimum metal utilization. It is also shown in a 250nm CMOS technology that there can be a significant electromagnetic signal coupling between the on-chip transmitting antenna and the metal interconnects on a die (-12.09dB for a 1.6mm long, 2μm wide interconnect at a distance of 1μm from the antenna). Design considerations are presented for the metal interconnects in the presence of on-chip antennas in order to minimize the undesired electromagnetic signal coupling.

Leakage current analysis for intra-chip wireless interconnects

A simulation-based feasibility study of an intra-chip wireless interconnect system is presented. The wireless interconnect system is modelled in a 250 nm standard complementary metal-oxide semiconductor (CMOS) technology operating at typical conditions. A finite element method (FEM) based 3-D full-wave solver is used to perform the electromagnetic field analysis. In the field analysis, the effects of the radiation of an intra-chip wireless interconnect system operating at 16 GHz on the circuit devices and local metal interconnects at arbitrary distances from the antennas are investigated. It is shown that the transmission gain between the antennas is mostly unaffected by the presence of local metal interconnects. The transmission scattering parameter (s-parameter) between the radiating antenna and the metal interconnects is below −31.66 dB. The leakage current in the sub-threshold region of the transistors, caused by the antenna radiation induced voltages, is shown to be below 2.2 fA and decreasing with distance from the radiating antenna.

A unified design methodology for a hybrid wireless 2-D NoC

Hybrid wireless NoCs are proposed to improve the communication throughput and energy compared to flat mesh-based NoCs. However, the multi-faceted design of a hybrid wireless NoC presents a conundrum amongst the different design paradigms. In this work, a methodology with minimal design complexity is presented for the design of hybrid wireless NoCs encompassing the different paradigms. To illustrate one use of the methodology, path loss models for the wireless channel implemented with various operating frequencies and substrate types are presented which are to be used in the design space exploration of the NoC.

Simulation Based Feasibility Study of Wireless RF Interconnects for 3D ICs

A feasibility study of inter-tier wireless interconnects to be used in conjunction with through silicon vias (TSVs) for global communication in 3D ICs is presented. The feasibility is shown by performing a full wave electromagnetic analysis of on-chip communicating antennas in a 3D IC, modeled according to a fully-depleted silicon on insulator (FDSOI) 3D circuit integration technology. It is shown that the selected transmitting and receiving antennas provide a strong signal coupling at the adjacent (-6.67 dB) and the non-adjacent (-6.93 dB) tiers of the 3D IC at a radiation frequency of 10GHz. In addition to permitting non-adjacent tier communication, wireless interconnects are superior to TSVs in permitting non-vertically aligned connections between IC tiers.

3-D Parasitic Modeling for Rotary Interconnects

Resonant rotary clocking is a high-frequency, low-power technology for high performance integrated circuits (IC). The implementation of the rotary clocking technology requires long interconnects with varying geometric shape segments on the chip, which are modeled by transmission lines. The parasitics exhibited by the transmission line interconnects play a major role in characterizing the high frequency operation. To this end, the impact of parasitics on the operating characteristics of the rotary rings due to the different interconnect segments are identified. The interconnect parasitics are analyzed using a 3D finite element method based full wave electromagnetic analysis. Simulations performed for the rotary ring with 3D full wave based parasitic analysis results in 23.68% reduced clock frequency when compared with a conventional 2D based parasitic analysis. The power dissipated on the rotary ring simulated using the 3D full wave based parasitic analysis is around 84% less than the clock tree and is within 5% of the power dissipated on the ring simulated using the 2D based parasitic analysis.

EM and circuit co-simulation of a reconfigurable hybrid wireless NoC on 2D ICs

The feasibility of the dynamic reconfigurability of the network layer of a hybrid wireless network-on-chip (NoC) that uses on-chip antennas for the wireless network layer and metal interconnects for the wired network layer is studied. The reconfigurability of the NoC is analyzed using a circuit co-simulation technique with a 3D finite element method (FEM) based full-wave electro-magnetic analysis of the antennas. The die and the circuits are modeled according to a typical complementary metal oxide semiconductor (CMOS) technology. It is shown that, it is possible to have 1) at least two different frequency domains for the signal sources and 2) the dynamic switching of the signal sinks between the two frequency domains, with minimal design and area overhead. When implemented, the proposed reconfigurable hybrid network architecture can reduce the latency and increase the network throughput.

Wireless NoCs Using Directional and Substrate Propagation Antennas

Wireless Network-on-Chip (WNoCs) are introduced to improve the performance for long distance communication within a chip. The on-chip antennas utilized in these WNoCs can be omni-directional or bi-directional, broadcasting to every receiving antenna or directional only in a specific pairing, respectively. There are positives and negatives for both types of antennas, although bi-directional antennas that do not cross paths have the added benefit of decreasing the possibility of interference. This work analyzes the performance of a WNoC with bi-directional antennas that uses an innovative substrate propagation technique recently introduced in literature. Antennas that use substrate propagation are capable of longer distance communication compared to typical on-chip antennas that use surface propagation. It is shown that by using the substrate propagation technique, wireless NoCs with minimal bi-directional antennas can reduce the number of wireless nodes by 66% while achieving similar performance of within ±5% of throughput.

Locality-Aware Network Utilization Balancing in NoCs

Hierarchical and multi-network networks-on-chip (NoCs) have been proposed in the literature to improve the energy- and performance-efficient scalability of the traditional flat-mesh NoC architecture. Theoretically, based on a small-world network-based analysis, traditional hierarchical NoCs are expected to provide good scalability. However, the traditional theoretical analysis (e.g. for small-worldness) does not take into account the congestion phenomenon experienced in such networks. Counterintuitively, as shown in this work, breaking the hierarchy in traditional hierarchical NoCs and utilizing the proposed locality-aware network utilization (NU) balancing technique performs better. This improvement in performance is observed through experimental analysis, which is contrasted with the theoretical analysis that does not account for congestion. In addition to the novelties for hierarchical networks, the application of the proposed locality-aware NU balancing scheme is extended to multi-network NoC topologies (with already separated networks). Results of the analysis show the superiority of applying the locality-aware NU balancing technique for a throughput and energy-efficient scaling of the multi-network NoC architectures, much like those of the hierarchical NoCs. For instance, for a NoC with 1024 nodes, the proposed NU balancing technique provides up to 95% higher throughput efficiency and consumes up to 29% less energy per flit compared to the best NoC topology without the NU balancing technique. The analysis also helps to render the choice of a NoC topology for traffic patterns varying in locality and nonlocality on exascale computing CMPs.