Baris Taskin

Timing Optimization Through Clock Skew Scheduling

This book details timing analysis and optimization techniques for circuits with level-sensitive memory elements. It contains a linear programming formulation applicable to the timing analysis of large scale circuits and includes a delay insertion methodology that improves the efficiency of clock skew scheduling. Coverage also provides a framework for and results from implementing timing optimization algorithms in a parallel computing environment.

Improving Line-Based QCA Memory Cell Design Through Dual Phase Clocking

This paper describes a line-based, quantum-dot cellular automata (QCA) memory cell design that is synchronized by a dual-phase clocking scheme. In line-based QCA memory cells, data bits are stored oscillating along QCA lines. The best known line-based memory cell implementation requires three new clocking zones in addition to the four clocking zones defined by the conventional QCA clocking scheme and utilizes three parallel clocking zones per cell. The proposed memory cell requires only two new clocking zones and utilizes two parallel clock zones per memory cell; permitting less CMOS circuity for clock design and denser QCA system implementations. Furthermore, read throughput is improved to one operation per clock cycle (from one read per two clock cycles). Simulations with the QCADesigner simulator are performed to verify the functionality of the proposed QCA memory cell.

Timing-Driven Physical Design for VLSI Circuits Using Resonant Rotary Clocking

Resonant clocking technologies are next-generation clocking technologies that provide low or controllable-skew, low-jitter and multi-gigahertz frequency clock signals with low power consumption. This paper describes a collection of circuit partitioning, placement and synchronization methodologies that enables the implementation of high speed, low power circuits synchronized with the resonant rotary clocking technology. Resonant rotary clocking technology inherently supports (and requires) non-zero clock skew operation, which permits further improved circuit performances. The proposed physical design flow entails integrated circuit partitioning and placement methodologies that permit the hierarchical application of non-zero clock skew system timing. This design flow is shown to be a computationally efficient implementation method.

Clock mesh synthesis with gated local trees and activity driven register clustering

A clock mesh network synthesis method is proposed which enables clock gating on the local sub-trees in order to reduce the clock power dissipation. Clock gating is performed with a register clustering strategy that considers both i) the similarity of switching activities between registers in a local area and ii) the timing slack on every local data path in the design. This is the first work known in literature that encapsulates the efficient implementation of the gated local trees and activity driven register clustering with timing slack awareness for clock mesh synthesis. Experimental results show that with gated local tree and activity driven register clustering, the switching capacitance on the mesh network can be reduced by 22% with limited skew degradation. The proposed method has two synthesis modes as low power mode and high performance mode to serve different design purposes.

Clock buffer polarity assignment considering capacitive load

A clock buffer polarity assignment method is proposed that considers the impact of capacitive load on the peak current. It is shown that the peak current on the supply rails of a buffer is a monotonically increasing function of its driving capacitance. Consequently, the polarity of a clock buffer is assigned based on its capacitive load. The proposed method can be applied to assign buffer polarity on any number of levels of the clock tree. In experiments, the peak current on the clock tree in each local area is reduced by 36.3% on average. The worse case peak current of all the local areas are reduced by 35.7% on average. The proposed method is implemented with a pseudo-polynomial dynamic programming scheme demonstrating runtimes under a minute.

Custom topology rotary clock router with tree subnetworks

Increasing demands on computing power have spurred the development of faster, higher-density Integrated Circuits (ICs), compounding power and complexity concerns in design budgets. The clock distribution network is a significant contributor to such power and complexity concerns. Resonant rotary clocking is a relatively new technology that realizes several benefits over current clocking methods, including power, frequency, and variation tolerance, yet lacks the automation tools to promote increased use. Towards this end, an automated rotary clock routing methodology is presented that generates custom topology rotary ring routes with tree subnetworks. In addition to the benefits of adiabatic clocking, the presented custom topology router permits 38.6% shorter wirelengths on average for register tapping, compared to traditional prescribed skew, binary tree routing.

Integrated Clock Mesh Synthesis With Incremental Register Placement

A clock mesh planning and synthesis method is proposed which significantly reduces the power dissipation on the network while considering the power density and timing slack simultaneously. The proposed method is performed at the postplacement stage and consists of three major steps: 1) feasible moving region construction of each register considering timing slack; 2) mesh grid wire generation and placement; and 3) incremental register placement for stub wire minimization considering power density and timing slack. The advantages of the proposed method are the reduced power dissipation-28% on average on the benchmark circuits-the optimized power density, and the guaranteed nonnegative timing slack. These advantages are possible through a decreased timing slack (1.1% of the clock period) and change in the logic wirelength (+5.9%) on the benchmark circuits.

Dual-Phase Line-Based QCA Memory Design

This paper describes a line-based, parallel-access QCA memory design that is synchronized by a dual-phase clocking scheme. In line-based QCA memories, data bits are stored propagating along acyclic QCA lines and additional clock generators are used to create the clocking zones of the memory regions. The memory design proposed in this paper requires an easy-to-implement, dual-phase clocking scheme. Dual-phase clocking is implemented with two clock phases which have the same duty cycle and are phase-shifted by half a clock cycle, thus, requiring only one additional clock generator. The number of clock zones per memory cell is reduced to a minimum of two, permitting denser memory implementations.

Steiner tree based rotary clock routing with bounded skew and capacitive load balancing

A novel rotary clock network routing method is proposed for the low-power resonant rotary clocking technology which guarantees: 1. The balanced capacitive load driven by each of the tapping points on the rotary rings, 2. Customized bounded clock skew among all the registers on chip, 3. A sub-optimally minimized total wirelength of the clock wire routes. In the proposed method, a forest of steiner trees is first created which connects the registers so as to achieve zero skew and greedily balance the total capacitance of each tree. Then, a balanced assignment of the steiner trees to the tapping points is performed to guarantee a balanced capacitive load on the rotary network. The proposed routing method is tested with the ISPD clock network contest and IBM r1–r5 benchmarks. The experimental results show that the capacitive load imbalance is very limited. The total wirelength is reduced by 64.2% compared to the best previous work known in literature through the combination of steiner tree routing and the assignment of trees to the tapping points. The average clock skew simulated using HSPICE is only 8.8ps when the bounded skew target is set to 10.0ps.

CROA: Design and Analysis of the Custom Rotary Oscillatory Array

Rotary clocking is a resonant clocking technology for clock network design and distribution in high performance digital VLSI circuits. Rotary clocking technology offers an attractive alternative to the conventional clocking with high frequency clock signal generation at a low power dissipation rate. Traditionally, rotary clocking has been implemented using a regular array (grid) topology called rotary oscillatory arrays (ROA). In this paper, a custom rotary oscillatory array (CROA) topology is proposed for the generation and distribution of rotary clocking. The issues related to timing closure are addressed and the simulation-based analysis of the custom rotary rings is presented. The CROA design methodology is tested on the IBM R1-R5 benchmark circuits. Compared to the traditional ROA, custom ROA results in 39.25% of tapping wirelength savings. The parasitic effects due to the customization of the topology - computed with partial element equivalent circuit (PEEC) analysis - are incorporated and the CROA topologies are simulated in SPICE. The simulation results show that, with additional parasitics due to the topological factors, the resultant clock frequency is observed to be 8.79% slower (assuming the tapping wirelength remains the same) than the expected frequency of operation without considering the topological factors.