Anshuman Chandra

Frequency-directed run-length (FDR) codes with application to system-on-a-chip test data compression

We showed recently that Golomb codes can be used for efficiently compressing system-on-a-chip test data. We now present a new class of variable-to-variable-length compression codes that are designed using the distributions of the runs of 0s in typical test sequences. We refer to these as frequency-directed run-length (FDR) codes. We present experimental results for the ISCAS 89 benchmark circuits to show that FDR codes outperform Golomb codes for test data compression. We also present a decompression architecture for FDR codes, and an analytical characterization of the amount of compression that can be expected using these codes. Analytical results show that FDR codes are robust, i.e. they are insensitive to variations in the input data stream.

Test data compression and test resource partitioning for system-on-a-chip using frequency-directed run-length (FDR) codes

Test data compression and test resource partitioning (TRP) are necessary to reduce the volume of test data for system-on-a-chip designs. We present a new class of variable-to-variable-length compression codes that are designed using distributions of the runs of 0s in typical test sequences. We refer to these as frequency-directed run-length (FDR) codes. We present experimental results for ISCAS 89 benchmark circuits and two IBM production circuits to show that FDR codes are extremely effective for test data compression and TRP. We derive upper and lower bounds on the compression expected for some generic parameters of the test sequences. These bounds are especially tight when the number of runs is small, thereby showing that FDR codes are robust, i.e., they are insensitive to variations in the input data stream. In order to highlight the inherent superiority of FDR codes, we present a probabilistic analysis of data compression for a memoryless data source. Finally, we derive entropy bounds for the benchmark test sets and show that the compression obtained using FDR codes is close to the entropy bounds.

Test data compression for system-on-a-chip using Golomb codes

We present a new test data compression method and decompression architecture based on Golomb codes. The proposed method is especially suitable for encoding precomputed test sets for embedded cores in a system-on-a-chip (SOC). The major advantages of Golomb codes include very high compression, analytically predictable compression results, and a low-cost and scalable on-chip decoder. In addition, the novel interleaving decompression architecture allows multiple cores in an SOC to be tested concurrently using a single ATE I/O channel. We demonstrate the effectiveness of the proposed approach by applying it to the ISCAS benchmark circuits and to two industrial production circuits. We also use analytical and experimental means to highlight the superiority of Golomb codes over run-length codes.

Reduction of SOC test data volume, scan power and testing time using alternating run-length codes

We present a test resource partitioning (TRP) technique that simultaneously reduces test data volume, test application time and scan power. The proposed approach is based on the use of alternating run-length codes for test data compression. Experimental results for the larger ISCAS-89 benchmarks and an IBM production circuit show that reduced test data volume, test application time and low power scan testing can indeed be achieved in all cases.

Low-power scan testing and test data compression for system-on-a-chip

Test data volume and power consumption for scan vectors are two major problems in system-on-a-chip testing. Since static compaction of scan vectors invariably leads to higher power for scan testing, the conflicting goals of low-power scan testing and reduced test data volume appear to be irreconcilable. We tackle this problem by using test data compression to reduce both test data volume and scan power. In particular, we show that Golomb coding of precomputed test sets leads to significant savings in peak and average power, without requiring either a slower scan clock or blocking logic in the scan cells. We also improve upon prior work on Golomb coding by showing that a separate cyclical scan register is not necessary for pattern decompression. Experimental results for the larger ISCAS 89 benchmarks show that reduced test data volume and low power scan testing can indeed be achieved in all cases.

Combining low-power scan testing and test data compression for system-on-a-chip

We present a novel technique to reduce both test data volume and scan power dissipation using test data compression for system-on-a-chip testing. Power dissipation during test mode using ATPG-compacted test patterns is much higher than during functional mode. We show that Golomb coding of precomputed test sets leads to significant savings in peak and average power, without requiring either a slower scan clock or blocking logic in the scan cells. We also improve upon prior work on Golomb coding by showing that a separate cyclical scan register is not necessary for pattern decompression. Experimental results for the larger ISCAS 89 benchmarks show that reduced test data volume and low power scan testing can indeed be achieved in all cases.

Test resource partitioning for SOCs

A new test-resource-partitioning approach, based on test data compression and on-chip decompression, reduces data volume, decreases testing time, and accommodates slower (less expensive) testers without decreasing test duality.

Test data compression and decompression based on internal scan chains and Golomb coding

We present a data compression method and decompression architecture for testing embedded cores in a system-on-a-chip (SOC). The proposed approach makes effective use of Golomb coding and the internal scan chain(s) of the core under test and provides significantly better results than a recent compression method that uses Golomb coding and a separate cyclical scan register (CSR). The major advantages of Golomb coding of test data include very high compression, analytically predictable compression results, and a low-cost and scalable on-chip decoder. The use of the internal scan chain for decompression obviates the need for a CSR, thereby reducing hardware overhead considerably. In addition, the novel interleaving decompression architecture allows multiple cores in an SOC to be tested concurrently using a single ATE I/O channel. We demonstrate the effectiveness of the proposed approach by. applying it to the ISCAS 89 benchmark circuits.

Bounded Adjacent Fill for Low Capture Power Scan Testing

Average and peak power dissipation can be reduced by controlling the switching activity in the scan chains during shift and capture cycles. In particular, minimum transition count or adjacent fill algorithm reduces transitions in the scan chains and has been shown to reduce average power dissipation during shift. In this paper, we show via statistical analysis of industrial circuits that contrary to conventional belief, scan-in and scan-out vectors are highly correlated for adjacent fill vectors. We also show that this correlation can be used to control the switching activity during the capture cycle. We propose a new filling algorithm called bounded adjacent fill that generates test vectors with low shift and capture switching activity and with no impact on pattern count.

Efficient test data compression and decompression for system-on-a-chip using internal scan chains and Golomb coding

We present a data compression method and decompression architecture for testing embedded cores in a system-on-a-chip (SOC). The proposed approach makes effective use of Golomb coding and the internal scan chains of the core under test, and provides significantly better results than a recent compression method that uses Golomb coding and a separate cyclical scan register (CSR). The use of the internal scan chain for decompression obviates the need for a CSR. In addition, the novel interleaving decompression architecture allows multiple cores in an SOC to be tested concurrently using a single ATE I/O channel. We demonstrate the effectiveness of the proposed approach by applying it to the ISCAS 89 benchmark circuits.