Anthony P. Ambler

Economic effects in design and test

The authors argue that because of misconceptions and myths about the cost of test, many devices and systems are inadequately tested. Focusing on application-specific integrated circuits (ASICs), the authors discuss the economics of test and show how economic analysis leads to test that pays back. The EVEREST test strategy planner, a design tool that aids in the selection of design-for-testability structures during ASIC design and uses cost as a primary selection parameter, is presented.<<ETX>>

Cost analysis of test method environments

As ICs get larger and increasingly more expensive to test, testing provision has to be made at the design stage. The authors discuss the development of a test-planning system based on economic considerations and using a parameterized economics model for cost predictions. The use of the economics model, as well as some of the factors that affect the cost effectiveness of design-for-test strategies are considered. Two levels of hierarchy in the cost modeling approach are discussed: the general model, which can be used to estimate costs from component design through to field test, and the component level, which addresses the modeling of component design, manufacture, and test costs.<<ETX>>

Test strategy planning using economic analysis

This article will discuss the impact on testing of life-cycle costs and present an approach for minimizing the overall life-cycle costs of a product by selecting the most economic test strategy at each stage. The selection of test strategy is based on a detailed economic analysis of the different test techniques available.

Sensitivity analysis in economics based test strategy planning

This article will present methods to analyze the sensitivity of test costs to the inaccuracy of the individual costing parameters. The results show that a few parameters—e.g., the gate count—need very detailed estimates, whereas the accuracy of many other parameters is insignificant in 99% of all cases. The techniques presented allow an in-depth evaluation of what is perceived as the main drawback in the use of economic modeling methods, namely, the element of risk associated with inaccuracies in the input data.

A STEADY-STATE RESPONSE TEST GENERATION FOR MIXED-SIGNAL INTEGRATED CIRCUITS

All s t r ac t A new approach to generate test vectors for Mixed-Signal Integrated Circuits (MS1C)s based on time response analysis is presented. The main objective is the development of a fast test generation to detect catastrophic faults in MSICs with keeping test overheads (chip area and pin count) at minimum.

Estimation of area and performance overheads for testable VLSI circuits

A method of estimating the area required to improve the testability of integrated circuits is described, and is illustrated by reference to programmable logic arrays (PLAs) with scan path applied. Parameters used in the models are derived from actual layouts. Results are given for PLAs with scan path, and for static RAMs incorporating scan path and built-in self-test (BIST) techniques. A stochastic model for estimating the global routing required on integrated circuits is presented, with results showing its use for predicting the routing area overhead due to test circuitry. A method of predicting the increased signal propagation delay due to added test circuitry is also given, together with the conditions for determining degradation in chip performance.<<ETX>>

Hierarchical testability measurement and design for test selection by cost prediction

Problems associated with test costs for complex electronic systems are discussed and a test strategy planner (TSP) is proposed which uses cost prediction throughout each design stage of a product to analyze the test costs and suggest methods of reducing the total product cost by design for test (DFT) choices. The TSP described is aimed at DFT applied to large integrated circuits designed within a standard-cell-based design system. However, the approach can be expanded both to encompass full-custom design of chips and to take in factors that affect board/system level implications of DFT at chip level.<<ETX>>

Economics in design and test

The issue of economics in design and test is a very troubled and turbulent one. Even amongst our accepted testability experts, there can be widely differing opinions as to the implications of design and test decisions at an economic level, e.g. the continuing debate on full scan vs. partial scan. The paper outlines some of the testability issues facing IC and system designers, especially the costs involved in making circuits testable.<<ETX>>