Chryssa Dislis

Economic effects in design and test

The authors argue that because of misconceptions and myths about the cost of test, many devices and systems are inadequately tested. Focusing on application-specific integrated circuits (ASICs), the authors discuss the economics of test and show how economic analysis leads to test that pays back. The EVEREST test strategy planner, a design tool that aids in the selection of design-for-testability structures during ASIC design and uses cost as a primary selection parameter, is presented.<<ETX>>

Cost analysis of test method environments

As ICs get larger and increasingly more expensive to test, testing provision has to be made at the design stage. The authors discuss the development of a test-planning system based on economic considerations and using a parameterized economics model for cost predictions. The use of the economics model, as well as some of the factors that affect the cost effectiveness of design-for-test strategies are considered. Two levels of hierarchy in the cost modeling approach are discussed: the general model, which can be used to estimate costs from component design through to field test, and the component level, which addresses the modeling of component design, manufacture, and test costs.<<ETX>>

Test strategy planning using economic analysis

This article will discuss the impact on testing of life-cycle costs and present an approach for minimizing the overall life-cycle costs of a product by selecting the most economic test strategy at each stage. The selection of test strategy is based on a detailed economic analysis of the different test techniques available.

Economics modelling for the determination of test strategies for complex VLSI boards

This paper describes the economics modeling techniques developed by the authors for the determination of optimal test strategies for board level testing. A number of interconnected economics models are used to describe the test process and the quality achieved, enabling the user to make predictive calculations for the effects of design and test choices. The results of sample runs presented, which illustrate the potential of the system as a decision making tool.<<ETX>>

Algorithms for cost optimised test strategy selection

This paper describes a system which aids designers in the selection of economically optimal design for testability strategies. The approach recognizes that design for testability decisions taken for parts of the circuit affect subsequent decisions for the design as a whole. Economics models are used to objectively evaluate strategies, and a set of algorithms is presented which provide efficient methods for searching the test strategy space. Different approaches are compared and a novel use of simulated annealing for test strategy planning is presented. Examples on real designs are given, with an indication of CPU time and computational complexity.<<ETX>>

Sensitivity analysis in economics based test strategy planning

This article will present methods to analyze the sensitivity of test costs to the inaccuracy of the individual costing parameters. The results show that a few parameters—e.g., the gate count—need very detailed estimates, whereas the accuracy of many other parameters is insignificant in 99% of all cases. The techniques presented allow an in-depth evaluation of what is perceived as the main drawback in the use of economic modeling methods, namely, the element of risk associated with inaccuracies in the input data.

Hierarchical testability measurement and design for test selection by cost prediction

Problems associated with test costs for complex electronic systems are discussed and a test strategy planner (TSP) is proposed which uses cost prediction throughout each design stage of a product to analyze the test costs and suggest methods of reducing the total product cost by design for test (DFT) choices. The TSP described is aimed at DFT applied to large integrated circuits designed within a standard-cell-based design system. However, the approach can be expanded both to encompass full-custom design of chips and to take in factors that affect board/system level implications of DFT at chip level.<<ETX>>

Economics in design and test

The issue of economics in design and test is a very troubled and turbulent one. Even amongst our accepted testability experts, there can be widely differing opinions as to the implications of design and test decisions at an economic level, e.g. the continuing debate on full scan vs. partial scan. The paper outlines some of the testability issues facing IC and system designers, especially the costs involved in making circuits testable.<<ETX>>