Anthony S. Oates

Electromigration Failure Distributions of Cu/Low-

We examine the effects of void morphology and critical current density (jc) on the electromigration failure distributions of Cu/low-k dual-damascene vias. Cu dual-damascene vias exhibit multiple modes of electromigration-induced voiding, and reliability is strongly dependent on the morphology of voids. We have developed a model of failure for dc and pulsed dc currents that allows prediction of failure time distributions for vias, taking into account void morphology. We obtain good agreement between the model predictions and experimental data for all observed void morphologies. The model demonstrates that while the concept of ldquoimmortalityrdquo is valid for individual conductors, it cannot be applied to eliminate failure of all nominally identical conductors in large sample sizes that are typical of integrated circuits. We experimentally confirm the existence of resistance increase failures for test populations of nominally identical conductors stressed below the sample average jc. Moreover, failure time distributions for vias exhibit distortion from lognormal and saturation in the vicinity of jc, but they are predictable for all values of j. New reliability extrapolation procedures are required for accurate projection of electromigration lifetimes close to jc. We suggest that the description of the effects of jc on failure distributions of vias discussed here is generally valid irrespective of the choice of conductor and barrier layer materials, and we demonstrate equivalent characteristic behavior of electromigration failure time distributions for both Al and Cu interconnects. Our results also indicate that, in general, accurate modeling of jc for conductor failure requires consideration of both nucleation and growth phenomena, with the relative contribution of each process to jc being dependent on the voiding failure mode.

k

The relative neutron-induced soft-error rate (SER) of bulk FinFET SRAMs compared to planar SRAMs is estimated based on drain area, collected charge, and critical charge using mixed-mode 3-D TCAD simulations. The critical charges of the bulk FinFET and planar devices are comparable, with identical gate length, gate width, and gate oxide thickness. However, the charges collected by the bulk FinFET drain due to ion strikes are smaller than those by the planar FET drain. Bulk FinFETs are anticipated to exhibit lower SER sensitivity compared to planar FETs.

Dual-Damascene Vias: Impact of the Critical Current Density and a New Reliability Extrapolation Methodology

Series resistance has become a serious obstacle inhibiting the performance of advanced CMOS devices. However, series resistance quantification in these same advanced CMOS devices is becoming exceedingly difficult. In this letter, we demonstrate a very simple series resistance extraction procedure which is derived only from the ratio of two linear ID-VG measurements. This approach has a verifiable accuracy check and is successfully used to extract the series resistance from several advanced devices. Furthermore, the validity of the assumptions used in this series resistance extraction procedure is examined and shown to be justified. In an attempt to further test the validity of this technique, several known external resistors were inserted in series with the device under test. The series resistance extraction procedure faithfully reproduces these known external resistances to within ±10%.

Neutron-Induced Charge Collection Simulation of Bulk FinFET SRAMs Compared With Conventional Planar SRAMs

In this study, we propose a systematic method to separate the hole trapping from measured V1 shift, thus giving the ideal interface trap generation behavior without measurement disturbance. Three stages of interface trap generation have been illustrated with the analytical H-H2 NBTI reaction-diffusion model, and the hole trapping has also been verified with its voltage-enhanced and temperature-insensitive properties. Finally, the PMOS device lifetime extrapolation without considering the hole trapping might lead to significant lifetime overestimation.

A Simple Series Resistance Extraction Methodology for Advanced CMOS Devices

Line edge roughness (LER) and via-line misalignment strongly impact the time-dependent breakdown of the low- k dielectrics used in nanometer IC technologies. In this paper, we investigate, theoretically and experimentally, the impact of the variability of geometry on breakdown. By considering the statistical distribution of thickness between adjacent conductors exhibiting LER, we show that the breakdown location is a function of voltage and occurs at the minimum dielectric thickness at high voltage, but moves to the median thickness at the low voltages. Using these concepts, we show that LER modifies the functional form of failure distributions, and leads to a systematic change in the Weibull with voltage. Accurate reliability analysis requires new reliability extrapolation methodologies to account for these effects. We show that the minimum dielectric thickness present on a test structure or on a circuit is readily determined from routine measurements of dielectric thickness between metal lines. We verify theoretical predictions using measurements of failure distributions of both via and line test structures. Finally, we have shown that LER can significantly modify the apparent field dependence of the failure time, leading to ambiguity in the interpretation of the experimentally determined field dependence.

Separation method of hole trapping and interface trap generation and their roles in NBTI reaction-diffusion model

This work accounts for the single-bit and multiple-cell upset phenomena due to neutron strikes in highly scaled SRAMs implemented in a Deep-N-well process. 3D TCAD simulations are used to explain test results, upset mechanisms and implications for ECC.

Geometric Variability of Nanoscale Interconnects and Its Impact on the Time-Dependent Breakdown of Cu/Low-

The influence of the contact-to-contact space on the ESD performance of multi-finger silicided ground-gate NMOS (GGNMOS) is investigated. We find that the conventional contact layout, which has short contact-to-contact space, induces current localization, and degrade the device ESD performance. Here we discuss how to design a ballast resistor for silicided multi-finger GGNMOS and show that lengthening the contact spacing can significantly improve device ESD performance (It2, HBM and MM). This improvement eliminates the short channel induced degradation of thin oxide device ESD

k

The authors present a comprehensive set of measurements to assess the impact of plasma processing induced damage on NBTI and hot carrier reliability as a function of technology scaling. The authors demonstrate for the first time that both hot carrier and NBTI are impacted similarly by device antenna ratio, transistor active area and gate oxide thickness, while failure distributions exhibit significant deviations from lognormal as a result of plasma damage. The authors develop a model to explain the observed experimental dependences and to accurately simulate failure distributions in the presence of plasma damage.

Dielectrics

We investigate the electromigration-induced void morphologies that dominate the reliability of Cu/low-k dual damascene vias. We observe that while voids form in both the upper and lower metal levels during electromigration stress, slit-type voids underneath vias fundamentally dominate the reliability of vias. Early failure distributions are common-place for Cu dual-damascene vias, and we show that multi-link structures are a necessary and efficient means to ensure that all potential voiding modes are characterized during accelerated testing. Additionally we find via reliability is a function of width of the stripe attached to vias, and electromigration must be investigated across a wide width range to ensure that the limiting geometry is correctly identified

Analysis of multiple cell upsets due to neutrons in SRAMs for a Deep-N-well process

The reduction of electromigration failure times with scaling presents a critical challenge for continued technology development. Electromigration failure is determined by void morphology and Cu drift velocity. Using observations of changes in these parameters, particularly the increase in drift velocity due to the increasingly polycrystalline Cu grain structure, we are able to accurately model trends in failure times between the 65 and 20 nm nodes. Below 20 nm failure times will continue to decrease, but at a faster rate at the low percentiles associated with circuit reliability. Metal capping to reduce interfacial diffusion of Cu has no impact on the drift velocity at the most advanced technology nodes. Control of Cu grain structure and development of electromigration resistant Cu alloys provide the most effective means of improving electromigration performance.