Shou-Chung Lee

Geometric Variability of Nanoscale Interconnects and Its Impact on the Time-Dependent Breakdown of Cu/Low-

Line edge roughness (LER) and via-line misalignment strongly impact the time-dependent breakdown of the low- k dielectrics used in nanometer IC technologies. In this paper, we investigate, theoretically and experimentally, the impact of the variability of geometry on breakdown. By considering the statistical distribution of thickness between adjacent conductors exhibiting LER, we show that the breakdown location is a function of voltage and occurs at the minimum dielectric thickness at high voltage, but moves to the median thickness at the low voltages. Using these concepts, we show that LER modifies the functional form of failure distributions, and leads to a systematic change in the Weibull with voltage. Accurate reliability analysis requires new reliability extrapolation methodologies to account for these effects. We show that the minimum dielectric thickness present on a test structure or on a circuit is readily determined from routine measurements of dielectric thickness between metal lines. We verify theoretical predictions using measurements of failure distributions of both via and line test structures. Finally, we have shown that LER can significantly modify the apparent field dependence of the failure time, leading to ambiguity in the interpretation of the experimentally determined field dependence.

k

We investigate the electromigration-induced void morphologies that dominate the reliability of Cu/low-k dual damascene vias. We observe that while voids form in both the upper and lower metal levels during electromigration stress, slit-type voids underneath vias fundamentally dominate the reliability of vias. Early failure distributions are common-place for Cu dual-damascene vias, and we show that multi-link structures are a necessary and efficient means to ensure that all potential voiding modes are characterized during accelerated testing. Additionally we find via reliability is a function of width of the stripe attached to vias, and electromigration must be investigated across a wide width range to ensure that the limiting geometry is correctly identified

Dielectrics

We show that processes used to fabricate advanced porous dielectrics can exhibit reliability approaching the intrinsic capability of the material. Combining this with simulations of failure distributions as a function of porosity and line edge roughness we demonstrate that failure times due to electrical breakdown rapidly decrease below k=2.3. The rapid failure time decrease is due to the statistical nature of increasing porosity (decreasing k), which leads to a shortening of the percolation path for dielectric breakdown. Continued scaling will require greater understanding of the breakdown impact on circuits as well as materials innovations to improve robustness.

Identification and Analysis of Dominant Electromigration Failure Modes in Copper/Low-K Dual Damascene Interconnects

We investigate the impact of porosity on the reliability of low-k dielectrics. We show that electric field enhancement around pores occurs and is significantly increased by Cu interaction, suggesting a new potential mechanism for breakdown of dielectrics at stress conditions. We develop of an analytic model to predict failure distribution parameters as a function of porosity and show that the model is in good agreement with measurements for porosity in the range of 5% to 40%. We explain why the field acceleration factor γ is a constant for all silica-based material according to percolation theory. We propose that the percolation path difference between high field and low field would make the field dependence on failure time become non-linear.

Reliability limitations to the scaling of porous low-k dielectrics

We propose a new methodology to de-convolute the intrinsic low-k material and interconnect geometric components from acceleration testing failure data, which allows a straightforward prediction of low-k failure time distributions at use conditions. Our analysis shows the intrinsic porous low-k failure time of Cu damascene interconnect will drop significantly when nominal Cu line spacing below 30 nm, with the influence of Cu geometric variability, low-k failure time further degraded depends on the lithography patterning technique used.

Fundamental understanding of porous low-k dielectric breakdown

We investigate porous low-k SiCOH under dynamic voltage stress to provide new insights into electrical breakdown. Our results are consistent with the existence of two breakdown mechanisms: the first is independent of trench barrier material and other processing details and is identical for DC, unipolar and high frequency bipolar (AC) stress. This mechanism appears to involve permanent physical damage to the dielectric. The second breakdown mechanism is dependent upon process conditions, and is evident only during low frequency bipolar stress. We discuss our findings in terms of breakdown due to the presence of Cu in the dielectric, charge trapping and bond breakage.

A new methodology for copper/low-k dielectric reliability prediction

We show that the mechanism of stress voiding in Cu/low-k vias is independent of width in the range 0.07 - 0.42 squarem. The resistance change associated with voiding shows saturation with stress time, implying that stress voiding is not a fundamental concern for continued feature size scaling. Stress voiding at narrow w is very sensitive to interconnect processing, and can give unexpected, large resistance increases with annealing.

Reliability of porous low-k dielectrics under dynamic voltage stressing

We investigate the voltage dependence of porous low-k dielectric breakdown. We show that interconnect geometric variability will affect both intrinsic Weibull slope (β) and field acceleration. We proposed a new method to verify the low-k electric field dependence that uses complete failure time distributions instead of single median time to fail values measured at different voltages. Our results show that both E and √E model can describe failure distributions for high and low test voltages, while the failure time data at low-voltages is inconsistent with the prediction from power law, impact damage, and 1/E models.

Characterization of stress-voiding of Cu / Low-k vias attached to narrow lines

We investigate the electric field (E) dependence of the breakdown of porous low-k dielectrics by measuring the changes in the failure time distribution resulting from the presence of line edge roughness. We show that the Weibull β increases with decreasing field, clearly demonstrating that dielectric breakdown does not exhibit 1/E or E-n characteristics.

On the voltage dependence of copper/low-k dielectric breakdown

We postulate that BEOL dielectric breakdown can be described by the nucleation and subsequent growth of percolation defects. We develop a semi-empirical model to describe the statistics of post-breakdown current growth and eventual hard breakdown. The model predicts experimentally accessible interconnect lengths will exhibit a Poisson length dependence of the time to hard breakdown, and a percentile-dependent length dependence of the growth time. At the low percentiles of failure time distributions relevant to circuit reliability, the growth time is independent of the interconnect length, and as a result the reliability of circuits is dominated entirely by growth times. These findings provide the basis of new methodology for prediction of dielectric reliability that exhibits substantial increases compared to current industry standard methods.