Anton Balaz

Data flow graph mapping techniques of computer architecture with data driven computation model

Article introduces architecture of computer with data driven computation model based on principles of tile computing which is modern approach to multi-core design of microprocessors, with basic principle of cores layout in bi-directional mesh of cores with interconnecting communication network. Special attention is paid to description of data flow graph mapping technique and multi-mapping techniques proposed within this architecture. Hardware implementation of computers prototype with use of Xilinx Spartan 3 PCIe Starter board with Spartan 3 AN FPGA chip is also described. Architecture is developed at the Department of Computers and Informatics, Faculty of Electrical Engineering and Informatics, Technical University of Kosice. The work is one of reached results within projects VEGA 1/4071/07 and APVV 0073–07, being solved at the Department of Computers and Informatics, Faculty of Electrical Engineering and Informatics, Technical University of Košice.

Distributed intrusion detection system using self organizing map

The goal of the article of to present intrusion detections system and design a two layer architecture of distributed intrusion detection based on the neural network self-organizing map. First layer consists of detection sensors which provide basic processing of input data on behalf of statistical methods with a direct connection to countermeasure modules. Performance and accuracy of the modeling system is ensured by using central distributed processing, in which the detection of generalized description with self-organizing map is used, preventing the intrusion itself.

Priority of instructions execution and DFG mapping techniques of computer architecture with data driven computation model

The article introduces proposed computer architecture with data driven computation model based on principles of tile computing as the modern approach to multi-core design of microprocessors. Special attention is paid to the description of characteristics of architecture, which are priority of instructions execution with coloring of instruction priorities, data flow graph mapping technique and multi-mapping technique, which are proposed within this architecture. Architecture is developed at the Department of Computers and Informatics, Faculty of Electrical Engineering and Informatics, Technical University of Košice. The work is one of reached results within projects APVV-0008-10 and KEGA project No. 3/7110/09, being solved at the Department of Computers and Informatics, Faculty of Electrical Engineering and Informatics, Technical University of Košice.

Architecture of Computer Intrusion Detection Based on Partially Ordered Events

Information technologies became part of our daily life. Nowadays, contemporary society is dependent on functioning of miscellaneous information systems providing daily community motion. The attack aim is often to disrupt, deny of service or at least one of its parts required for proper functionality, or to acquire unauthorized access to information [Vokorokos (2004)]. Nowadays, solid system assecuration becomes one of the main priorities. Basic way of protection is realized through specialized devices firewalls allowing to define and control permitted communications in boundary parts of computer network or between protected segments and surrounding environment. Present firewalls often detect some unauthorized attack activities but their functionality is limited. Unauthorized intrusion detection systems allow increase of information systems security against attacks from the Internet or organization intranet, by means of passive inform about arising intrusion or active interfere against defecting intrusion. The existing intrusion detection approaches can be divided in two classes anomaly detection and misuse detection [Denning (1987)]. The anomaly detection approaches the problem by attempting to find deviations from the established patterns of usage. On the other hand, the misuse detection compares the usage patterns to known techniques of compromising computer security. Architecturally, the intrusion detection system(IDS) can be categorized into three types host-based IDS, network-based IDS and hybrid IDS [Bace (2000)]. The host-based IDS, deployed in individual host-machines, can monitor audit data of a single host. The network-based IDS monitors the traffic data sent and received by hosts. The hybrid IDS uses bothmethods. The intrusion detection throughmultiple sources represents a difficult task. Intrusion pattern matching has a non-deterministic nature where that same intrusion or attack can be realized through various permutations of the same events. The purpose of this paper is to present authors’ proposed intrusion detection architecture based on the partially ordered events and the Petri nets. Project is proposed and implemented at the Department of Computers and Informatics in Kosice supported by VEGA 1/4071/07. (Security architecture of heterogeneous distributed and parallel computing system and dynamical computing system resistant against attacks) a APVV 0073-07 (Identification methods and analysis of safety threats in architecture of distributed computer systems and dynamical networks).

Artificial neural network based IDS

The Network Intrusion Detection Systems (NIDS) are either signature based or anomaly based. In this paper presented NIDS system belongs to anomaly based Neural Network Intrusion Detection System (NNIDS). The proposed NNIDS is able to successfully recognize learned malicious activities in a network environment. It was tested for the SYN flood attack, UDP flood attack, nMap scanning attack, and also for non-malicious communication.

Security sandbox based on RBAC model

The article presents a security solution of mapping RBAC model in to Linux kernel systems. RBAC management model represents an effective concept of mapping user organization structure to access control of computer systems objects. Definition of RBAC model roles allows declaring permitted operations with specified security policy. Based on the roles, system management model provides a comprehensive system protection against security threats and misuse of user credentials. The result of this paper is a set of defined roles forming security sandboxes within defined security policies of particular roles.

Intrusion detection system based on partially ordered events and patterns

The purpose of this paper is to present intrusion detection systems (IDS) and proposed architecture of the IDS based on partially ordered events and patterns. The article describes problematic of intrusion detection systems and intrusions detection. Furthermore the paper considers concrete design of IDS architecture based on intrusion signatures. The core of the presented architecture is intrusion signature matching through Petri Nets that classify monitored system behavior and determine intrusion of monitored computer system. The paper result is a new detection method and a new architecture of intrusion detection system.

The CASE tool for programming of the multi-core System-on-a-Chip with the data flow computation control

The paper describes Computer Aided Software Engineering (CASE) tool, that supports programming of the experimental multi-core tile based System-on-a-Chip (SoC). SoC comprises cores, which are based on the data flow computation control principle. Proposed CASE tool allows creation of the program code in graphical form using Data Flow Graph (DFG) or in text representation using assembly language or machine code. Automatic transformations between those representations are supported. CASE tool brings sequential, mask based and global multi-mapping of the program code, which was introduced in our previous research. Another output lies in introduction of altered assembly language and machine code that allow multi-mapping of the program code on the instructions level. The aim of the solution lies in optimization of the program load phase in multi-core microprocessors that comprise tens or potentially hundreds of cores.

Agent-Based Model of the Spectrum Auctions with Sensing Imperfections in Dynamic Spectrum Access Networks

Cognitive radio (CR) is the underlying platform for the application of dynamic spectrum access (DSA) networks. Although the auction theory and spectrum trading mechanisms have been discussed in the CR related works, their joint techno-economic impact on the efficiency of distributed CR networks has not been researched yet. In this paper we assume heterogeneous primary channels with network availability statistics unknown to each secondary user (SU) terminal. In order to detect the idle primary user (PU) network channels, the SU terminals trigger regularly the spectrum sensing mechanism and make the cooperative decision regarding the channel status at the fusion center. The imperfections of the spectrum mechanism create the possibility of the channel collision, resulting in the existence of the risk (in terms of user collision) in the network. The spectrum trading within SU network is governed by the application of the sealed-bid first-price auction, which takes into account the channel valuation as well as the statistical probability of the risk existence. In order to maximize the long-term payoff, the SU terminals take an advantage of the reinforcement comparison strategy. The results demonstrate that in the investigated model, total revenue and total payoff of the SU operator (auctioneer) and SU terminals (bidders) are characterized by the existence of the global optimum, thus there exists the optimal sensing time guaranteeing the optimum economic factors for both SU operator and SU terminals.